Lines Matching full:clkgen
188 clocks = <&clkgen JH7100_CLK_SDIO0_AHB>,
189 <&clkgen JH7100_CLK_SDIO0_CCLKINT_INV>;
201 clocks = <&clkgen JH7100_CLK_SDIO1_AHB>,
202 <&clkgen JH7100_CLK_SDIO1_CCLKINT_INV>;
214 clocks = <&clkgen JH7100_CLK_GMAC_ROOT_DIV>,
215 <&clkgen JH7100_CLK_GMAC_AHB>,
216 <&clkgen JH7100_CLK_GMAC_PTP_REF>,
217 <&clkgen JH7100_CLK_GMAC_TX_INV>,
218 <&clkgen JH7100_CLK_GMAC_GTX>;
242 clkgen: clock-controller@11800000 { label
243 compatible = "starfive,jh7100-clkgen";
264 clocks = <&clkgen JH7100_CLK_I2C0_CORE>,
265 <&clkgen JH7100_CLK_I2C0_APB>;
277 clocks = <&clkgen JH7100_CLK_I2C1_CORE>,
278 <&clkgen JH7100_CLK_I2C1_APB>;
292 clocks = <&clkgen JH7100_CLK_GPIO_APB>;
304 clocks = <&clkgen JH7100_CLK_UART2_CORE>,
305 <&clkgen JH7100_CLK_UART2_APB>;
317 clocks = <&clkgen JH7100_CLK_UART3_CORE>,
318 <&clkgen JH7100_CLK_UART3_APB>;
330 clocks = <&clkgen JH7100_CLK_I2C2_CORE>,
331 <&clkgen JH7100_CLK_I2C2_APB>;
343 clocks = <&clkgen JH7100_CLK_I2C3_CORE>,
344 <&clkgen JH7100_CLK_I2C3_APB>;
356 clocks = <&clkgen JH7100_CLK_WDTIMER_APB>,
357 <&clkgen JH7100_CLK_WDT_CORE>;
366 clocks = <&clkgen JH7100_CLK_PWM_APB>;
375 clocks = <&clkgen JH7100_CLK_TEMP_SENSE>,
376 <&clkgen JH7100_CLK_TEMP_APB>;