Lines Matching +full:0 +full:x10010000
18 #size-cells = <0>;
20 U74_0: cpu@0 {
22 reg = <0>;
118 #clock-cells = <0>;
121 clock-frequency = <0>;
126 #clock-cells = <0>;
129 clock-frequency = <0>;
134 #clock-cells = <0>;
137 clock-frequency = <0>;
142 #clock-cells = <0>;
145 clock-frequency = <0>;
158 reg = <0x0 0x2000000 0x0 0x10000>;
165 reg = <0x0 0x2010000 0x0 0x1000>;
175 compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0";
176 reg = <0x0 0xc000000 0x0 0x4000000>;
180 #address-cells = <0>;
187 reg = <0x0 0x10000000 0x0 0x10000>;
192 data-addr = <0>;
200 reg = <0x0 0x10010000 0x0 0x10000>;
205 data-addr = <0>;
213 reg = <0x0 0x10020000 0x0 0x10000>;
227 starfive,syscon = <&sysmain 0x70 0>;
238 snps,blen = <256 128 64 32 0 0 0>;
244 reg = <0x0 0x11800000 0x0 0x10000>;
252 reg = <0x0 0x11840000 0x0 0x10000>;
258 reg = <0x0 0x11850000 0x0 0x10000>;
263 reg = <0x0 0x118b0000 0x0 0x10000>;
270 #size-cells = <0>;
276 reg = <0x0 0x118c0000 0x0 0x10000>;
283 #size-cells = <0>;
289 reg = <0x0 0x11910000 0x0 0x10000>,
290 <0x0 0x11858000 0x0 0x1000>;
303 reg = <0x0 0x12430000 0x0 0x10000>;
316 reg = <0x0 0x12440000 0x0 0x10000>;
329 reg = <0x0 0x12450000 0x0 0x10000>;
336 #size-cells = <0>;
342 reg = <0x0 0x12460000 0x0 0x10000>;
349 #size-cells = <0>;
355 reg = <0x0 0x12480000 0x0 0x10000>;
365 reg = <0x0 0x12490000 0x0 0x10000>;
374 reg = <0x0 0x124a0000 0x0 0x10000>;
381 #thermal-sensor-cells = <0>;