dts/sophgo/cv18xx.dtsi

1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/clock/sophgo,cv1800.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
12 	#address-cells = <1>;
13 	#size-cells = <1>;
16 		#address-cells = <1>;
17 		#size-cells = <0>;
18 		timebase-frequency = <25000000>;
24 			d-cache-block-size = <64>;
25 			d-cache-sets = <512>;
26 			d-cache-size = <65536>;
27 			i-cache-block-size = <64>;
28 			i-cache-sets = <128>;
29 			i-cache-size = <32768>;
30 			mmu-type = "riscv,sv39";
32 			riscv,isa-base = "rv64i";
33 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
36 			cpu0_intc: interrupt-controller {
37 				compatible = "riscv,cpu-intc";
38 				interrupt-controller;
39 				#interrupt-cells = <1>;
45 		compatible = "fixed-clock";
46 		clock-output-names = "osc_25m";
47 		#clock-cells = <0>;
51 		compatible = "simple-bus";
52 		interrupt-parent = <&plic>;
53 		#address-cells = <1>;
54 		#size-cells = <1>;
55 		dma-noncoherent;
58 		clk: clock-controller@3002000 {  label
61 			#clock-cells = <1>;
65 			compatible = "snps,dw-apb-gpio";
67 			#address-cells = <1>;
68 			#size-cells = <0>;
70 			porta: gpio-controller@0 {
71 				compatible = "snps,dw-apb-gpio-port";
72 				gpio-controller;
73 				#gpio-cells = <2>;
76 				interrupt-controller;
77 				#interrupt-cells = <2>;
83 			compatible = "snps,dw-apb-gpio";
85 			#address-cells = <1>;
86 			#size-cells = <0>;
88 			portb: gpio-controller@0 {
89 				compatible = "snps,dw-apb-gpio-port";
90 				gpio-controller;
91 				#gpio-cells = <2>;
94 				interrupt-controller;
95 				#interrupt-cells = <2>;
101 			compatible = "snps,dw-apb-gpio";
103 			#address-cells = <1>;
104 			#size-cells = <0>;
106 			portc: gpio-controller@0 {
107 				compatible = "snps,dw-apb-gpio-port";
108 				gpio-controller;
109 				#gpio-cells = <2>;
112 				interrupt-controller;
113 				#interrupt-cells = <2>;
119 			compatible = "snps,dw-apb-gpio";
121 			#address-cells = <1>;
122 			#size-cells = <0>;
124 			portd: gpio-controller@0 {
125 				compatible = "snps,dw-apb-gpio-port";
126 				gpio-controller;
127 				#gpio-cells = <2>;
130 				interrupt-controller;
131 				#interrupt-cells = <2>;
137 			compatible = "snps,designware-i2c";
139 			#address-cells = <1>;
140 			#size-cells = <0>;
141 			clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C0>;
142 			clock-names = "ref", "pclk";
148 			compatible = "snps,designware-i2c";
150 			#address-cells = <1>;
151 			#size-cells = <0>;
152 			clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C1>;
153 			clock-names = "ref", "pclk";
159 			compatible = "snps,designware-i2c";
161 			#address-cells = <1>;
162 			#size-cells = <0>;
163 			clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C2>;
164 			clock-names = "ref", "pclk";
170 			compatible = "snps,designware-i2c";
172 			#address-cells = <1>;
173 			#size-cells = <0>;
174 			clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C3>;
175 			clock-names = "ref", "pclk";
181 			compatible = "snps,designware-i2c";
183 			#address-cells = <1>;
184 			#size-cells = <0>;
185 			clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C4>;
186 			clock-names = "ref", "pclk";
192 			compatible = "snps,dw-apb-uart";
195 			clocks = <&clk CLK_UART0>, <&clk CLK_APB_UART0>;
196 			clock-names = "baudclk", "apb_pclk";
197 			reg-shift = <2>;
198 			reg-io-width = <4>;
203 			compatible = "snps,dw-apb-uart";
206 			clocks = <&clk CLK_UART1>, <&clk CLK_APB_UART1>;
207 			clock-names = "baudclk", "apb_pclk";
208 			reg-shift = <2>;
209 			reg-io-width = <4>;
214 			compatible = "snps,dw-apb-uart";
217 			clocks = <&clk CLK_UART2>, <&clk CLK_APB_UART2>;
218 			clock-names = "baudclk", "apb_pclk";
219 			reg-shift = <2>;
220 			reg-io-width = <4>;
225 			compatible = "snps,dw-apb-uart";
228 			clocks = <&clk CLK_UART3>, <&clk CLK_APB_UART3>;
229 			clock-names = "baudclk", "apb_pclk";
230 			reg-shift = <2>;
231 			reg-io-width = <4>;
236 			compatible = "snps,dw-apb-ssi";
238 			#address-cells = <1>;
239 			#size-cells = <0>;
240 			clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI0>;
241 			clock-names = "ssi_clk", "pclk";
247 			compatible = "snps,dw-apb-ssi";
249 			#address-cells = <1>;
250 			#size-cells = <0>;
251 			clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI1>;
252 			clock-names = "ssi_clk", "pclk";
258 			compatible = "snps,dw-apb-ssi";
260 			#address-cells = <1>;
261 			#size-cells = <0>;
262 			clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI2>;
263 			clock-names = "ssi_clk", "pclk";
269 			compatible = "snps,dw-apb-ssi";
271 			#address-cells = <1>;
272 			#size-cells = <0>;
273 			clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI3>;
274 			clock-names = "ssi_clk", "pclk";
280 			compatible = "snps,dw-apb-uart";
283 			clocks = <&clk CLK_UART4>, <&clk CLK_APB_UART4>;
284 			clock-names = "baudclk", "apb_pclk";
285 			reg-shift = <2>;
286 			reg-io-width = <4>;
291 			compatible = "sophgo,cv1800b-dwcmshc";
294 			clocks = <&clk CLK_AXI4_SD0>,
295 				 <&clk CLK_SD0>;
296 			clock-names = "core", "bus";
300 		dmac: dma-controller@4330000 {
301 			compatible = "snps,axi-dma-1.01a";
304 			clocks = <&clk CLK_SDMA_AXI>, <&clk CLK_SDMA_AXI>;
305 			clock-names = "core-clk", "cfgr-clk";
306 			#dma-cells = <1>;
307 			dma-channels = <8>;
308 			snps,block-size = <1024 1024 1024 1024
311 			snps,dma-masters = <2>;
312 			snps,data-width = <4>;
316 		plic: interrupt-controller@70000000 {
318 			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
319 			interrupt-controller;
320 			#address-cells = <0>;
321 			#interrupt-cells = <2>;
327 			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;