arch/riscv/Kconfig.errata

20 	  non-standard handling on non-coherent operations on Andes cores.
22 	  If you don't know what to do here, say "Y".
35 	bool "Apply SiFive errata CIP-453"
39 	  This will apply the SiFive CIP-453 errata to add sign extension
43 	  If you don't know what to do here, say "Y".
46 	bool "Apply SiFive errata CIP-1200"
50 	  This will apply the SiFive CIP-1200 errata to repalce all
54 	  If you don't know what to do here, say "Y".
68 	  caches that are non-coherent with respect to peripheral DMAs.
69 	  It was designed before the Zicbom extension so needs non-standard
76 	bool "T-HEAD errata"
79 	  All T-HEAD errata Kconfig depend on this Kconfig. Disabling
80 	  this Kconfig will disable all T-HEAD errata. Please say "Y"
81 	  here if your platform uses T-HEAD CPU cores.
86 	bool "Apply T-Head's memory attribute extension (XTheadMae) errata"
92 	  non-standard PTE utilization on T-Head SoCs (XTheadMae).
94 	  If you don't know what to do here, say "Y".
97 	bool "Apply T-Head cache management errata"
105 	  non-standard handling on non-coherent operations on T-Head SoCs.
107 	  If you don't know what to do here, say "Y".
110 	bool "Apply T-Head PMU errata"
114 	  The T-Head C9xx cores implement a PMU overflow extension very
117 	  This will apply the overflow errata to handle the non-standard
120 	  If you don't know what to do here, say "Y".