4  * Copyright (c) 1999-2001 Dan Malek <dan@embeddedalley.com>
54 #define CPM_MAP_SIZE	(0x40000)	/* 256k - the PQ3 reserve this amount
55 					   of space for CPM as it is larger
68 	cpmp = &cpm2_immr->im_cpm;  in cpm2_reset()
71 	/* Reset the CPM.  in cpm2_reset()
81 int cpm_command(u32 command, u8 opcode)  in cpm_command()  argument
89 	out_be32(&cpmp->cp_cpcr, command | opcode | CPM_CR_FLG);  in cpm_command()
91 		if ((in_be32(&cpmp->cp_cpcr) & CPM_CR_FLG) == 0)  in cpm_command()
94 	printk(KERN_ERR "%s(): Not able to issue CPM command\n", __func__);  in cpm_command()
95 	ret = -EIO;  in cpm_command()
103  * eight BRGs, which can be connected to the CPM channels or output
109  * Baud rate clocks are zero-based in the driver code (as that maps
110  * to port numbers).  Documentation uses 1-based numbering.
120 		bp = &cpm2_immr->im_brgc1;  in __cpm2_setbrg()
122 		bp = &cpm2_immr->im_brgc5;  in __cpm2_setbrg()
123 		brg -= 4;  in __cpm2_setbrg()
127 	val = (((clk * 2 / rate) - 1) & ~1) | CPM_BRG_EN | src;  in __cpm2_setbrg()
204 		reg = &cpm2_immr->im_cpmux.cmx_scr;  in cpm2_clk_setup()
208 		reg = &cpm2_immr->im_cpmux.cmx_scr;  in cpm2_clk_setup()
212 		reg = &cpm2_immr->im_cpmux.cmx_scr;  in cpm2_clk_setup()
216 		reg = &cpm2_immr->im_cpmux.cmx_scr;  in cpm2_clk_setup()
220 		reg = &cpm2_immr->im_cpmux.cmx_fcr;  in cpm2_clk_setup()
224 		reg = &cpm2_immr->im_cpmux.cmx_fcr;  in cpm2_clk_setup()
228 		reg = &cpm2_immr->im_cpmux.cmx_fcr;  in cpm2_clk_setup()
233 		return -EINVAL;  in cpm2_clk_setup()
243 	    ret = -EINVAL;  in cpm2_clk_setup()
282 		reg = &cpm2_immr->im_cpmux.cmx_smr;  in cpm2_smc_clk_setup()
287 		reg = &cpm2_immr->im_cpmux.cmx_smr;  in cpm2_smc_clk_setup()
293 		return -EINVAL;  in cpm2_smc_clk_setup()
303 	    ret = -EINVAL;  in cpm2_smc_clk_setup()
321 		(struct cpm2_ioports __iomem *)&cpm2_immr->im_ioport;  in cpm2_set_pin()
323 	pin = 1 << (31 - pin);  in cpm2_set_pin()