Lines Matching +full:0 +full:x0c08
36 SPE_TYPE_LOGICAL = 0,
46 u8 padding_0140[0x0140];
47 u64 int_status_class0_RW; /* 0x0140 */
48 u64 int_status_class1_RW; /* 0x0148 */
49 u64 int_status_class2_RW; /* 0x0150 */
50 u8 padding_0158[0x0610-0x0158];
51 u64 mfc_dsisr_RW; /* 0x0610 */
52 u8 padding_0618[0x0620-0x0618];
53 u64 mfc_dar_RW; /* 0x0620 */
54 u8 padding_0628[0x0800-0x0628];
55 u64 mfc_dsipr_R; /* 0x0800 */
56 u8 padding_0808[0x0810-0x0808];
57 u64 mfc_lscrr_R; /* 0x0810 */
58 u8 padding_0818[0x0c00-0x0818];
59 u64 mfc_cer_R; /* 0x0c00 */
60 u8 padding_0c08[0x0f00-0x0c08];
61 u64 spe_execution_status; /* 0x0f00 */
62 u8 padding_0f08[0x1000-0x0f08];
76 SPE_EX_STATE_UNEXECUTABLE = 0,
233 return 0; in setup_areas()
246 0, &spu->irqs[0]); in setup_interrupts()
268 ps3_spe_irq_destroy(spu->irqs[0]); in setup_interrupts()
270 spu->irqs[0] = spu->irqs[1] = spu->irqs[2] = 0; in setup_interrupts()
297 return 0; in enable_spu()
302 lv1_disable_logical_spe(spu_pdata(spu)->spe_id, 0); in enable_spu()
313 result = lv1_disable_logical_spe(spu_pdata(spu)->spe_id, 0); in ps3_destroy_spu()
318 ps3_spe_irq_destroy(spu->irqs[0]); in ps3_destroy_spu()
320 spu->irqs[0] = spu->irqs[1] = spu->irqs[2] = 0; in ps3_destroy_spu()
330 return 0; in ps3_destroy_spu()
351 spu_pdata(spu)->cache.sr1 = 0x33; in ps3_create_spu()
370 (void)0; in ps3_create_spu()
397 for (i = 0; i < num_resource_id; i++) { in ps3_enumerate_spus()
426 return 0; in ps3_init_affinity()
496 stat, 0); in int_stat_clear()
579 return 0; /* No support. */ in resource_allocation_groupID_get()
589 return 0; /* No support. */ in resource_allocation_enable_get()