Lines Matching +full:- +full:single +full:- +full:end
1 // SPDX-License-Identifier: GPL-2.0-or-later
13 * The majority of the complexity in supporting SR-IOV on PowerNV comes from
20 * the address range that we want to map to be power-of-two sized and aligned.
24 * For a SR-IOV BAR things are a little more awkward since size and alignment
25 * are not coupled. The alignment is set based on the per-VF BAR size, but
26 * the total BAR area is: number-of-vfs * per-vf-size. The number of VFs
29 * allocate the SR-IOV BARs in a way that lets us map them using the MBT.
32 * of MBT entry that we use. We only support SR-IOV on PHB3 (IODA2) and above,
40 * b) An un-segmented BAR that maps the whole address range to a specific PE.
43 * We prefer to use mode a) since it only requires one MBT entry per SR-IOV BAR
44 * For comparison b) requires one entry per-VF per-BAR, or:
45 * (num-vfs * num-sriov-bars) in total. To use a) we need the size of each segment
46 * to equal the size of the per-VF BAR area. So:
48 * new_size = per-vf-size * number-of-PEs
50 * The alignment for the SR-IOV BAR also needs to be changed from per-vf-size
57 * but no resource allocations have been done. The SR-IOV BARs are sized
72 * Our hook overrides the default alignment, equal to the per-vf-size, with
82 * MBT mapping for each SR-IOV BAR. In steps 1) and 2) we setup an "arena"
84 * around the actual SR-IOV BAR location within this arena. We need this
90 * the address programmed into the SR-IOV BAR of the PF so that the address
102 * move SR-IOV resource back to its "proper" location.
104 * That's how mode a) works. In theory mode b) (single PE mapping) is less work
109 * it only usable for devices with very large per-VF BARs. Such devices are
113 * 16 total and some are needed for. Most SR-IOV capable network cards can support
121 * PHB4 (IODA3) added a few new features that would be useful for SR-IOV. It
123 * us to support SR-IOV BARs in the 32bit MMIO window. This is useful since
124 * the Linux BAR allocation will place any BAR marked as non-prefetchable into
125 * the non-prefetchable bridge window, which is 32bit only. It also added two
145 struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); in pnv_pci_ioda_fixup_iov_resources()
155 pdev->dev.archdata.iov_data = iov; in pnv_pci_ioda_fixup_iov_resources()
156 mul = phb->ioda.total_pe_num; in pnv_pci_ioda_fixup_iov_resources()
159 res = &pdev->resource[i + PCI_IOV_RESOURCES]; in pnv_pci_ioda_fixup_iov_resources()
160 if (!res->flags || res->parent) in pnv_pci_ioda_fixup_iov_resources()
162 if (!pnv_pci_is_m64_flags(res->flags)) { in pnv_pci_ioda_fixup_iov_resources()
163 dev_warn(&pdev->dev, "Don't support SR-IOV with non M64 VF BAR%d: %pR. \n", in pnv_pci_ioda_fixup_iov_resources()
172 * if a VF BAR is too large we end up wasting a lot of space. in pnv_pci_ioda_fixup_iov_resources()
174 * then each VF BAR should be mapped in single-PE mode to reduce in pnv_pci_ioda_fixup_iov_resources()
180 if (vf_bar_sz > (phb->ioda.m64_segsize >> 2)) { in pnv_pci_ioda_fixup_iov_resources()
183 * single mode is 32MB. If this VF BAR is smaller than in pnv_pci_ioda_fixup_iov_resources()
185 * then we can't map it and need to disable SR-IOV for in pnv_pci_ioda_fixup_iov_resources()
189 pci_err(pdev, "VF BAR%d: %pR can't be mapped in single PE mode\n", in pnv_pci_ioda_fixup_iov_resources()
194 iov->m64_single_mode[i] = true; in pnv_pci_ioda_fixup_iov_resources()
203 res->end = res->start + vf_bar_sz * mul - 1; in pnv_pci_ioda_fixup_iov_resources()
209 iov->need_shift = true; in pnv_pci_ioda_fixup_iov_resources()
217 res = &pdev->resource[i + PCI_IOV_RESOURCES]; in pnv_pci_ioda_fixup_iov_resources()
218 res->flags = 0; in pnv_pci_ioda_fixup_iov_resources()
219 res->end = res->start - 1; in pnv_pci_ioda_fixup_iov_resources()
222 pdev->dev.archdata.iov_data = NULL; in pnv_pci_ioda_fixup_iov_resources()
228 if (pdev->is_virtfn) { in pnv_pci_ioda_fixup_iov()
232 * VF PEs are single-device PEs so their pdev pointer needs to in pnv_pci_ioda_fixup_iov()
236 pe->pdev = pdev; in pnv_pci_ioda_fixup_iov()
237 WARN_ON(!(pe->flags & PNV_IODA_PE_VF)); in pnv_pci_ioda_fixup_iov()
238 } else if (pdev->is_physfn) { in pnv_pci_ioda_fixup_iov()
251 struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); in pnv_pci_iov_resource_alignment()
255 * iov can be null if we have an SR-IOV device with IOV BAR that can't in pnv_pci_iov_resource_alignment()
256 * be placed in the m64 space (i.e. The BAR is 32bit or non-prefetch). in pnv_pci_iov_resource_alignment()
264 * If we're using single mode then we can just use the native VF BAR in pnv_pci_iov_resource_alignment()
265 * alignment. We validated that it's possible to use a single PE in pnv_pci_iov_resource_alignment()
268 if (iov->m64_single_mode[resno - PCI_IOV_RESOURCES]) in pnv_pci_iov_resource_alignment()
273 * SR-IOV. While from hardware perspective, the range mapped by M64 in pnv_pci_iov_resource_alignment()
278 * If the M64 BAR is in Single PE mode, return the VF BAR size or in pnv_pci_iov_resource_alignment()
281 return phb->ioda.total_pe_num * align; in pnv_pci_iov_resource_alignment()
290 phb = pci_bus_to_pnvhb(pdev->bus); in pnv_pci_vf_release_m64()
293 for_each_set_bit(window_id, iov->used_m64_bar_mask, MAX_M64_BARS) { in pnv_pci_vf_release_m64()
294 opal_pci_phb_mmio_enable(phb->opal_id, in pnv_pci_vf_release_m64()
299 clear_bit(window_id, &phb->ioda.m64_bar_alloc); in pnv_pci_vf_release_m64()
308 * is subdivided into phb->ioda.total_pe_num segments and there's a 1-1
318 rc = opal_pci_set_phb_mem_window(phb->opal_id, in pnv_ioda_map_m64_segmented()
327 rc = opal_pci_phb_mmio_enable(phb->opal_id, in pnv_ioda_map_m64_segmented()
348 * with P7-IOC in mind. For that chip each M64 BAR (window) had a fixed in pnv_ioda_map_m64_single()
354 * a problem for p7-ioc since you didn't have a choice, but the in pnv_ioda_map_m64_single()
355 * single PE windows added in PHB3 don't map cleanly to this API. in pnv_ioda_map_m64_single()
358 * call opal_pci_map_pe_mmio_window() to put the single in single in pnv_ioda_map_m64_single()
360 * bounds. We need to do it this way because the single PE windows in pnv_ioda_map_m64_single()
363 rc = opal_pci_map_pe_mmio_window(phb->opal_id, in pnv_ioda_map_m64_single()
372 * NB: In single PE mode the window needs to be aligned to 32MB in pnv_ioda_map_m64_single()
374 rc = opal_pci_set_phb_mem_window(phb->opal_id, in pnv_ioda_map_m64_single()
378 0, /* ignored by FW, m64 is 1-1 */ in pnv_ioda_map_m64_single()
384 * Now actually enable it. We specified the BAR should be in "non-split" in pnv_ioda_map_m64_single()
385 * mode so FW will validate that the BAR is in single PE mode. in pnv_ioda_map_m64_single()
387 rc = opal_pci_phb_mmio_enable(phb->opal_id, in pnv_ioda_map_m64_single()
393 pr_err("Error mapping single PE BAR\n"); in pnv_ioda_map_m64_single()
403 win = find_next_zero_bit(&phb->ioda.m64_bar_alloc, in pnv_pci_alloc_m64_bar()
404 phb->ioda.m64_bar_idx + 1, 0); in pnv_pci_alloc_m64_bar()
406 if (win >= phb->ioda.m64_bar_idx + 1) in pnv_pci_alloc_m64_bar()
407 return -1; in pnv_pci_alloc_m64_bar()
408 } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc)); in pnv_pci_alloc_m64_bar()
410 set_bit(win, iov->used_m64_bar_mask); in pnv_pci_alloc_m64_bar()
426 phb = pci_bus_to_pnvhb(pdev->bus); in pnv_pci_vf_assign_m64()
430 res = &pdev->resource[i + PCI_IOV_RESOURCES]; in pnv_pci_vf_assign_m64()
431 if (!res->flags || !res->parent) in pnv_pci_vf_assign_m64()
434 /* don't need single mode? map everything in one go! */ in pnv_pci_vf_assign_m64()
435 if (!iov->m64_single_mode[i]) { in pnv_pci_vf_assign_m64()
441 start = res->start; in pnv_pci_vf_assign_m64()
450 /* otherwise map each VF with single PE BARs */ in pnv_pci_vf_assign_m64()
452 base_pe_num = iov->vf_pe_arr[0].pe_number; in pnv_pci_vf_assign_m64()
459 start = res->start + size * j; in pnv_pci_vf_assign_m64()
472 return -EBUSY; in pnv_pci_vf_assign_m64()
480 phb = pci_bus_to_pnvhb(pdev->bus); in pnv_ioda_release_vf_PE()
482 if (!pdev->is_physfn) in pnv_ioda_release_vf_PE()
486 list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) { in pnv_ioda_release_vf_PE()
487 if (pe->parent_dev != pdev) in pnv_ioda_release_vf_PE()
493 mutex_lock(&phb->ioda.pe_list_mutex); in pnv_ioda_release_vf_PE()
494 list_del(&pe->list); in pnv_ioda_release_vf_PE()
495 mutex_unlock(&phb->ioda.pe_list_mutex); in pnv_ioda_release_vf_PE()
511 if (!dev->is_physfn) in pnv_pci_vf_resource_shift()
512 return -EINVAL; in pnv_pci_vf_resource_shift()
523 num_vfs = iov->num_vfs; in pnv_pci_vf_resource_shift()
525 res = &dev->resource[i + PCI_IOV_RESOURCES]; in pnv_pci_vf_resource_shift()
526 if (!res->flags || !res->parent) in pnv_pci_vf_resource_shift()
528 if (iov->m64_single_mode[i]) in pnv_pci_vf_resource_shift()
538 res2.flags = res->flags; in pnv_pci_vf_resource_shift()
539 res2.start = res->start + (size * offset); in pnv_pci_vf_resource_shift()
540 res2.end = res2.start + (size * num_vfs) - 1; in pnv_pci_vf_resource_shift()
542 if (res2.end > res->end) { in pnv_pci_vf_resource_shift()
543 …dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n", in pnv_pci_vf_resource_shift()
545 return -EBUSY; in pnv_pci_vf_resource_shift()
558 res = &dev->resource[i + PCI_IOV_RESOURCES]; in pnv_pci_vf_resource_shift()
559 if (!res->flags || !res->parent) in pnv_pci_vf_resource_shift()
561 if (iov->m64_single_mode[i]) in pnv_pci_vf_resource_shift()
566 res->start += size * offset; in pnv_pci_vf_resource_shift()
568 dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n", in pnv_pci_vf_resource_shift()
573 devm_release_resource(&dev->dev, &iov->holes[i]); in pnv_pci_vf_resource_shift()
574 memset(&iov->holes[i], 0, sizeof(iov->holes[i])); in pnv_pci_vf_resource_shift()
580 iov->holes[i].start = res2.start; in pnv_pci_vf_resource_shift()
581 iov->holes[i].end = res2.start + size * offset - 1; in pnv_pci_vf_resource_shift()
582 iov->holes[i].flags = IORESOURCE_BUS; in pnv_pci_vf_resource_shift()
583 iov->holes[i].name = "pnv_iov_reserved"; in pnv_pci_vf_resource_shift()
584 devm_request_resource(&dev->dev, res->parent, in pnv_pci_vf_resource_shift()
585 &iov->holes[i]); in pnv_pci_vf_resource_shift()
600 num_vfs = iov->num_vfs; in pnv_pci_sriov_disable()
601 base_pe = iov->vf_pe_arr[0].pe_number; in pnv_pci_sriov_disable()
606 /* Un-shift the IOV BARs if we need to */ in pnv_pci_sriov_disable()
607 if (iov->need_shift) in pnv_pci_sriov_disable()
608 pnv_pci_vf_resource_shift(pdev, -base_pe); in pnv_pci_sriov_disable()
623 if (!pdev->is_physfn) in pnv_ioda_setup_vf_PE()
626 phb = pci_bus_to_pnvhb(pdev->bus); in pnv_ioda_setup_vf_PE()
636 pe = &iov->vf_pe_arr[vf_index]; in pnv_ioda_setup_vf_PE()
637 pe->phb = phb; in pnv_ioda_setup_vf_PE()
638 pe->flags = PNV_IODA_PE_VF; in pnv_ioda_setup_vf_PE()
639 pe->pbus = NULL; in pnv_ioda_setup_vf_PE()
640 pe->parent_dev = pdev; in pnv_ioda_setup_vf_PE()
641 pe->mve_number = -1; in pnv_ioda_setup_vf_PE()
642 pe->rid = (vf_bus << 8) | vf_devfn; in pnv_ioda_setup_vf_PE()
644 pe_num = pe->pe_number; in pnv_ioda_setup_vf_PE()
646 pci_domain_nr(pdev->bus), pdev->bus->number, in pnv_ioda_setup_vf_PE()
652 pe->pdev = NULL; in pnv_ioda_setup_vf_PE()
657 mutex_lock(&phb->ioda.pe_list_mutex); in pnv_ioda_setup_vf_PE()
658 list_add_tail(&pe->list, &phb->ioda.pe_list); in pnv_ioda_setup_vf_PE()
659 mutex_unlock(&phb->ioda.pe_list_mutex); in pnv_ioda_setup_vf_PE()
662 list_for_each_entry(vf_pdn, &pdn->parent->child_list, list) { in pnv_ioda_setup_vf_PE()
663 if (vf_pdn->busno == vf_bus && in pnv_ioda_setup_vf_PE()
664 vf_pdn->devfn == vf_devfn) { in pnv_ioda_setup_vf_PE()
665 vf_pdn->pe_number = pe_num; in pnv_ioda_setup_vf_PE()
682 phb = pci_bus_to_pnvhb(pdev->bus); in pnv_pci_sriov_enable()
692 if (phb->type != PNV_PHB_IODA2) { in pnv_pci_sriov_enable()
693 pci_err(pdev, "SR-IOV is not supported on this PHB\n"); in pnv_pci_sriov_enable()
694 return -ENXIO; in pnv_pci_sriov_enable()
698 dev_info(&pdev->dev, "don't support this SRIOV device with non 64bit-prefetchable IOV BAR\n"); in pnv_pci_sriov_enable()
699 return -ENOSPC; in pnv_pci_sriov_enable()
706 return -EBUSY; in pnv_pci_sriov_enable()
709 iov->vf_pe_arr = base_pe; in pnv_pci_sriov_enable()
710 iov->num_vfs = num_vfs; in pnv_pci_sriov_enable()
715 dev_info(&pdev->dev, "Not enough M64 window resources\n"); in pnv_pci_sriov_enable()
724 if (iov->need_shift) { in pnv_pci_sriov_enable()
725 ret = pnv_pci_vf_resource_shift(pdev, base_pe->pe_number); in pnv_pci_sriov_enable()
740 pnv_ioda_free_pe(&iov->vf_pe_arr[i]); in pnv_pci_sriov_enable()