206 #define kw_write_reg(reg, val)	__kw_write_reg(host, reg, val)  macro
234 	kw_write_reg(reg_control, KW_I2C_CTL_STOP);  in kw_i2c_do_stop()
250 		kw_write_reg(reg_isr, isr);  in kw_i2c_handle_interrupt()
263 			kw_write_reg(reg_status, 0);  in kw_i2c_handle_interrupt()
265 		kw_write_reg(reg_ier, 0x00);  in kw_i2c_handle_interrupt()
287 					kw_write_reg(reg_control,  in kw_i2c_handle_interrupt()
291 				kw_write_reg(reg_data, *(host->data++));  in kw_i2c_handle_interrupt()
295 		kw_write_reg(reg_isr, KW_I2C_IRQ_ADDR);  in kw_i2c_handle_interrupt()
302 			kw_write_reg(reg_isr, KW_I2C_IRQ_DATA);  in kw_i2c_handle_interrupt()
306 				kw_write_reg(reg_control, 0);  in kw_i2c_handle_interrupt()
314 				kw_write_reg(reg_data, *(host->data++));  in kw_i2c_handle_interrupt()
323 		kw_write_reg(reg_isr, KW_I2C_IRQ_DATA);  in kw_i2c_handle_interrupt()
327 		kw_write_reg(reg_isr, KW_I2C_IRQ_STOP);  in kw_i2c_handle_interrupt()
339 		kw_write_reg(reg_isr, KW_I2C_IRQ_START);  in kw_i2c_handle_interrupt()
425 	kw_write_reg(reg_isr, kw_read_reg(reg_isr));  in kw_i2c_xfer()
426 	kw_write_reg(reg_mode, mode_reg | (bus->channel << 4));  in kw_i2c_xfer()
427 	kw_write_reg(reg_status, 0);  in kw_i2c_xfer()
432 	kw_write_reg(reg_addr, addrdir & 0xff);  in kw_i2c_xfer()
437 		kw_write_reg(reg_subaddr, subaddr);  in kw_i2c_xfer()
454 		kw_write_reg(reg_isr, kw_read_reg(reg_isr));  in kw_i2c_xfer()
459 		kw_write_reg(reg_ier, KW_I2C_IRQ_MASK);  in kw_i2c_xfer()
463 	kw_write_reg(reg_control, KW_I2C_CTL_XADDR);  in kw_i2c_xfer()
480 	kw_write_reg(reg_ier, 0);  in kw_i2c_xfer()
547 	kw_write_reg(reg_ier, 0);  in kw_i2c_host_init()