164 	unsigned long		fcr;  in ohare_htw_scc_enable()  local
190 		fcr = MACIO_IN32(OHARE_FCR);  in ohare_htw_scc_enable()
192 		if (!(fcr & OH_SCC_ENABLE)) {  in ohare_htw_scc_enable()
193 			fcr |= OH_SCC_ENABLE;  in ohare_htw_scc_enable()
201 					fcr &= ~HRW_SCC_TRANS_EN_N;  in ohare_htw_scc_enable()
202 				MACIO_OUT32(OHARE_FCR, fcr);  in ohare_htw_scc_enable()
203 				fcr |= (rmask = HRW_RESET_SCC);  in ohare_htw_scc_enable()
204 				MACIO_OUT32(OHARE_FCR, fcr);  in ohare_htw_scc_enable()
206 				fcr |= (rmask = OH_SCC_RESET);  in ohare_htw_scc_enable()
207 				MACIO_OUT32(OHARE_FCR, fcr);  in ohare_htw_scc_enable()
213 			fcr &= ~rmask;  in ohare_htw_scc_enable()
214 			MACIO_OUT32(OHARE_FCR, fcr);  in ohare_htw_scc_enable()
217 			fcr |= OH_SCCA_IO;  in ohare_htw_scc_enable()
219 			fcr |= OH_SCCB_IO;  in ohare_htw_scc_enable()
220 		MACIO_OUT32(OHARE_FCR, fcr);  in ohare_htw_scc_enable()
229 		fcr = MACIO_IN32(OHARE_FCR);  in ohare_htw_scc_enable()
231 			fcr &= ~OH_SCCA_IO;  in ohare_htw_scc_enable()
233 			fcr &= ~OH_SCCB_IO;  in ohare_htw_scc_enable()
234 		MACIO_OUT32(OHARE_FCR, fcr);  in ohare_htw_scc_enable()
235 		if ((fcr & (OH_SCCA_IO | OH_SCCB_IO)) == 0) {  in ohare_htw_scc_enable()
236 			fcr &= ~OH_SCC_ENABLE;  in ohare_htw_scc_enable()
238 				fcr |= HRW_SCC_TRANS_EN_N;  in ohare_htw_scc_enable()
239 			MACIO_OUT32(OHARE_FCR, fcr);  in ohare_htw_scc_enable()
604 	u32			fcr;  in core99_scc_enable()  local
621 		fcr = MACIO_IN32(KEYLARGO_FCR0);  in core99_scc_enable()
623 		if (!(fcr & KL0_SCC_CELL_ENABLE)) {  in core99_scc_enable()
624 			fcr |= KL0_SCC_CELL_ENABLE;  in core99_scc_enable()
628 			fcr |= KL0_SCCA_ENABLE;  in core99_scc_enable()
631 				fcr &= ~KL0_SCC_A_INTF_ENABLE;  in core99_scc_enable()
633 				fcr |= KL0_SCC_A_INTF_ENABLE;  in core99_scc_enable()
636 			fcr |= KL0_SCCB_ENABLE;  in core99_scc_enable()
639 				fcr &= ~KL0_SCC_B_INTF_ENABLE;  in core99_scc_enable()
640 				fcr |= KL0_IRDA_ENABLE;  in core99_scc_enable()
641 				fcr |= KL0_IRDA_CLK32_ENABLE | KL0_IRDA_CLK19_ENABLE;  in core99_scc_enable()
642 				fcr |= KL0_IRDA_SOURCE1_SEL;  in core99_scc_enable()
643 				fcr &= ~(KL0_IRDA_FAST_CONNECT|KL0_IRDA_DEFAULT1|KL0_IRDA_DEFAULT0);  in core99_scc_enable()
644 				fcr &= ~(KL0_IRDA_SOURCE2_SEL|KL0_IRDA_HIGH_BAND);  in core99_scc_enable()
647 				fcr |= KL0_SCC_B_INTF_ENABLE;  in core99_scc_enable()
649 		MACIO_OUT32(KEYLARGO_FCR0, fcr);  in core99_scc_enable()
674 		fcr = MACIO_IN32(KEYLARGO_FCR0);  in core99_scc_enable()
676 			fcr &= ~KL0_SCCA_ENABLE;  in core99_scc_enable()
678 			fcr &= ~KL0_SCCB_ENABLE;  in core99_scc_enable()
681 				fcr &= ~KL0_IRDA_ENABLE;  in core99_scc_enable()
682 				fcr &= ~(KL0_IRDA_CLK32_ENABLE | KL0_IRDA_CLK19_ENABLE);  in core99_scc_enable()
683 				fcr &= ~(KL0_IRDA_FAST_CONNECT|KL0_IRDA_DEFAULT1|KL0_IRDA_DEFAULT0);  in core99_scc_enable()
684 				fcr &= ~(KL0_IRDA_SOURCE1_SEL|KL0_IRDA_SOURCE2_SEL|KL0_IRDA_HIGH_BAND);  in core99_scc_enable()
687 		MACIO_OUT32(KEYLARGO_FCR0, fcr);  in core99_scc_enable()
688 		if ((fcr & (KL0_SCCA_ENABLE | KL0_SCCB_ENABLE)) == 0) {  in core99_scc_enable()
689 			fcr &= ~KL0_SCC_CELL_ENABLE;  in core99_scc_enable()
690 			MACIO_OUT32(KEYLARGO_FCR0, fcr);  in core99_scc_enable()