platforms/powermac/cache.S

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3  * This file contains low-level cache management functions
5  * (In fact the only thing that is Apple-specific is that we assume
15 #include <asm/feature-fixups.h>
45 	sync
52 	sync
58 	sync
60 	sync
62 	/* Disp-flush L1. We have a weird problem here that I never
64 	 * results in a non-working flush. We use that workaround for
65 	 * now until I finally understand what's going on. --BenH
81 	sync
88 	sync
91 	sync
96 	sync
100 	/* Set to data-only (pre-745x bit) */
102 	b	2f
106 3:	sync
109 2:	b	3f
110 3:	sync
113 1:	/* disp-flush L2. The interesting thing here is that the L2 can be
114 	 * up to 2Mb ... so using the ROM, we'll end up wrapping back to memory
115 	 * but that is probbaly fine. We disp-flush over 4Mb to be safe
117 	lis	r4,2
123 	sync
125 	lis	r4,2
131 	sync
136 	b	2f
140 3:	sync
143 2:	b	3f
144 3:	sync
147 1:	sync
149 	/* Invalidate L2. This is pre-745x, we clear the L2I bit ourselves */
152 	sync
162 	sync
164 	sync
170 	sync
174 	sync
178 	sync
181 	sync
195 	sync
201 	sync
207 	sync
239         sync
253 	sync
255 2:	lwz	r0,0(r3)	/* touch each cache line */
257 	bdnz	2b
265 	sync
267 	sync
275 	b	2f
279 3:	sync
282 2:	b	3f
283 3:	sync
286 1:	sync
289 	sync
294 	sync
296 	b	2f
300 3:	sync
303 2:	b	3f
304 3:	sync
307 1:	sync
311 	sync
316 	sync
325 	sync
327 	sync
330 	sync
336 	sync
338 	sync
344 	sync
350 	sync