1 // SPDX-License-Identifier: GPL-2.0
19 #include <asm/pci-bridge.h>
30  * The VLSI Golden Gate II has only 512K of PCI configuration space, so we
40 	if (bus->number > 7)  in gg2_read_config()
43 	 * Note: the caller has already checked that off is  in gg2_read_config()
46 	cfg_data = hose->cfg_data + ((bus->number<<16) | (devfn<<8) | off);  in gg2_read_config()
67 	if (bus->number > 7)  in gg2_write_config()
70 	 * Note: the caller has already checked that off is  in gg2_write_config()
73 	cfg_data = hose->cfg_data + ((bus->number<<16) | (devfn<<8) | off);  in gg2_write_config()
102 		| (((bus->number - hose->first_busno) & 0xff) << 16)  in rtas_read_config()
103 		| (hose->global_number << 24);  in rtas_read_config()
104         int ret = -1;  in rtas_read_config()
117 		| (((bus->number - hose->first_busno) & 0xff) << 16)  in rtas_write_config()
118 		| (hose->global_number << 24);  in rtas_write_config()
139 	np = of_find_node_by_name(NULL, "mac-io");  in hydra_init()
148 	       in_le32(&Hydra->Feature_Control));  in hydra_init()
149 	out_le32(&Hydra->Feature_Control, (HYDRA_FC_SCC_CELL_EN |  in hydra_init()
157 	printk(", now %x\n", in_le32(&Hydra->Feature_Control));  in hydra_init()
175 	/* Clear the magic go-slow bit */  in setup_python()
196 		hose->ops = &rtas_pci_ops;  in setup_peg2()
211 	int len, index = -1;  in chrp_find_bridges()
242 		bus_range = of_get_property(dev, "bus-range", &len);  in chrp_find_bridges()
244 			printk(KERN_WARNING "Can't get bus-range for %pOF\n",  in chrp_find_bridges()
264 		hose->first_busno = hose->self_busno = bus_range[0];  in chrp_find_bridges()
265 		hose->last_busno = bus_range[1];  in chrp_find_bridges()
277 			hose->ops = &gg2_pci_ops;  in chrp_find_bridges()
278 			hose->cfg_data = p;  in chrp_find_bridges()
290 				dma = of_get_property(dev, "system-dma-base",  in chrp_find_bridges()
295 						len - sizeof(*dma));  in chrp_find_bridges()
302 			hose->ops = &rtas_pci_ops;  in chrp_find_bridges()
309 		dma = of_get_property(dev, "ibm,dma-ranges", &len);  in chrp_find_bridges()
311 			pci_dram_offset = dma[2] - dma[3];  in chrp_find_bridges()
319 	 *  -- Geert  in chrp_find_bridges()
331  * ATA controller to be set to fully native mode or bad things
338 	/* If non-briq machines need that fixup too, please speak up */  in chrp_pci_fixup_winbond_ata()
342 	if ((sl82c105->class & 5) != 5) {  in chrp_pci_fixup_winbond_ata()
343 		printk("W83C553: Switching SL82C105 IDE to PCI native mode\n");  in chrp_pci_fixup_winbond_ata()
344 		/* Enable SL82C105 PCI native IDE mode */  in chrp_pci_fixup_winbond_ata()
347 		sl82c105->class |= 0x05;  in chrp_pci_fixup_winbond_ata()
360 /* Pegasos2 firmware version 20040810 configures the built-in IDE controller
361  * in legacy mode, but sets the PCI registers to PCI native mode.
362  * The chip can only operate in legacy mode, so force the PCI class into legacy
363  * mode as well. The same fixup must be done to the class-code property in
373 	if (viaide->irq != 14)  in chrp_pci_fixup_vt8231_ata()
379 	dev_info(&viaide->dev, "Fixing VIA IDE, force legacy mode on\n");  in chrp_pci_fixup_vt8231_ata()
383 	viaide->class &= ~0x5;  in chrp_pci_fixup_vt8231_ata()