Lines Matching +full:gpio +full:- +full:dir
1 // SPDX-License-Identifier: GPL-2.0
27 #include <linux/dma-mapping.h>
48 #include <linux/gpio/legacy-of-mm-gpiochip.h>
58 cpmp = &mpc8xx_immr->im_cpm; in cpm_reset()
62 out_be16(&cpmp->cp_cpcr, CPM_CR_RST | CPM_CR_FLG); in cpm_reset()
65 while (in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG); in cpm_reset()
80 out_be32(&mpc8xx_immr->im_siu_conf.sc_sdcr, 0x40); in cpm_reset()
82 out_be32(&mpc8xx_immr->im_siu_conf.sc_sdcr, 1); in cpm_reset()
95 return -EINVAL; in cpm_command()
100 out_be16(&cpmp->cp_cpcr, command | CPM_CR_FLG | (opcode << 8)); in cpm_command()
102 if ((in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG) == 0) in cpm_command()
106 ret = -EIO; in cpm_command()
129 bp = &cpmp->cp_brgc1; in cpm_setbrg()
132 * The BRG has a 12-bit counter. For really slow baud rates (or in cpm_setbrg()
135 if (((BRG_UART_CLK / rate) - 1) < 4096) in cpm_setbrg()
136 out_be32(bp, (((BRG_UART_CLK / rate) - 1) << 1) | CPM_BRG_EN); in cpm_setbrg()
138 out_be32(bp, (((BRG_UART_CLK_DIV16 / rate) - 1) << 1) | in cpm_setbrg()
144 __be16 dir, par, odr_sor, dat, intr; member
149 __be32 dir, par, odr, dat; member
153 __be32 dir, par, sor, odr, dat; member
159 pin = 1 << (31 - pin); in cpm1_set_pin32()
163 &mpc8xx_immr->im_cpm.cp_pbdir; in cpm1_set_pin32()
166 &mpc8xx_immr->im_cpm.cp_pedir; in cpm1_set_pin32()
169 setbits32(&iop->dir, pin); in cpm1_set_pin32()
171 clrbits32(&iop->dir, pin); in cpm1_set_pin32()
174 setbits32(&iop->par, pin); in cpm1_set_pin32()
176 clrbits32(&iop->par, pin); in cpm1_set_pin32()
180 setbits16(&mpc8xx_immr->im_cpm.cp_pbodr, pin); in cpm1_set_pin32()
182 clrbits16(&mpc8xx_immr->im_cpm.cp_pbodr, pin); in cpm1_set_pin32()
187 setbits32(&iop->sor, pin); in cpm1_set_pin32()
189 clrbits32(&iop->sor, pin); in cpm1_set_pin32()
192 setbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin); in cpm1_set_pin32()
194 clrbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin); in cpm1_set_pin32()
201 (struct cpm_ioport16 __iomem *)&mpc8xx_immr->im_ioport; in cpm1_set_pin16()
203 pin = 1 << (15 - pin); in cpm1_set_pin16()
206 iop += port - 1; in cpm1_set_pin16()
209 setbits16(&iop->dir, pin); in cpm1_set_pin16()
211 clrbits16(&iop->dir, pin); in cpm1_set_pin16()
214 setbits16(&iop->par, pin); in cpm1_set_pin16()
216 clrbits16(&iop->par, pin); in cpm1_set_pin16()
220 setbits16(&iop->odr_sor, pin); in cpm1_set_pin16()
222 clrbits16(&iop->odr_sor, pin); in cpm1_set_pin16()
226 setbits16(&iop->odr_sor, pin); in cpm1_set_pin16()
228 clrbits16(&iop->odr_sor, pin); in cpm1_set_pin16()
230 setbits16(&iop->intr, pin); in cpm1_set_pin16()
232 clrbits16(&iop->intr, pin); in cpm1_set_pin16()
309 reg = &mpc8xx_immr->im_cpm.cp_sicr; in cpm1_clk_setup()
314 reg = &mpc8xx_immr->im_cpm.cp_sicr; in cpm1_clk_setup()
319 reg = &mpc8xx_immr->im_cpm.cp_sicr; in cpm1_clk_setup()
324 reg = &mpc8xx_immr->im_cpm.cp_sicr; in cpm1_clk_setup()
329 reg = &mpc8xx_immr->im_cpm.cp_simode; in cpm1_clk_setup()
334 reg = &mpc8xx_immr->im_cpm.cp_simode; in cpm1_clk_setup()
340 return -EINVAL; in cpm1_clk_setup()
352 return -EINVAL; in cpm1_clk_setup()
358 if (reg == &mpc8xx_immr->im_cpm.cp_sicr) { in cpm1_clk_setup()
374 * GPIO LIB API implementation
393 struct cpm_ioport16 __iomem *iop = mm_gc->regs; in cpm1_gpio16_save_regs()
395 cpm1_gc->cpdata = in_be16(&iop->dat); in cpm1_gpio16_save_regs()
398 static int cpm1_gpio16_get(struct gpio_chip *gc, unsigned int gpio) in cpm1_gpio16_get() argument
401 struct cpm_ioport16 __iomem *iop = mm_gc->regs; in cpm1_gpio16_get()
404 pin_mask = 1 << (15 - gpio); in cpm1_gpio16_get()
406 return !!(in_be16(&iop->dat) & pin_mask); in cpm1_gpio16_get()
412 struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc); in __cpm1_gpio16_set()
413 struct cpm_ioport16 __iomem *iop = mm_gc->regs; in __cpm1_gpio16_set()
416 cpm1_gc->cpdata |= pin_mask; in __cpm1_gpio16_set()
418 cpm1_gc->cpdata &= ~pin_mask; in __cpm1_gpio16_set()
420 out_be16(&iop->dat, cpm1_gc->cpdata); in __cpm1_gpio16_set()
423 static void cpm1_gpio16_set(struct gpio_chip *gc, unsigned int gpio, int value) in cpm1_gpio16_set() argument
426 struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc); in cpm1_gpio16_set()
428 u16 pin_mask = 1 << (15 - gpio); in cpm1_gpio16_set()
430 spin_lock_irqsave(&cpm1_gc->lock, flags); in cpm1_gpio16_set()
434 spin_unlock_irqrestore(&cpm1_gc->lock, flags); in cpm1_gpio16_set()
437 static int cpm1_gpio16_to_irq(struct gpio_chip *gc, unsigned int gpio) in cpm1_gpio16_to_irq() argument
440 struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc); in cpm1_gpio16_to_irq()
442 return cpm1_gc->irq[gpio] ? : -ENXIO; in cpm1_gpio16_to_irq()
445 static int cpm1_gpio16_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) in cpm1_gpio16_dir_out() argument
448 struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc); in cpm1_gpio16_dir_out()
449 struct cpm_ioport16 __iomem *iop = mm_gc->regs; in cpm1_gpio16_dir_out()
451 u16 pin_mask = 1 << (15 - gpio); in cpm1_gpio16_dir_out()
453 spin_lock_irqsave(&cpm1_gc->lock, flags); in cpm1_gpio16_dir_out()
455 setbits16(&iop->dir, pin_mask); in cpm1_gpio16_dir_out()
458 spin_unlock_irqrestore(&cpm1_gc->lock, flags); in cpm1_gpio16_dir_out()
463 static int cpm1_gpio16_dir_in(struct gpio_chip *gc, unsigned int gpio) in cpm1_gpio16_dir_in() argument
466 struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc); in cpm1_gpio16_dir_in()
467 struct cpm_ioport16 __iomem *iop = mm_gc->regs; in cpm1_gpio16_dir_in()
469 u16 pin_mask = 1 << (15 - gpio); in cpm1_gpio16_dir_in()
471 spin_lock_irqsave(&cpm1_gc->lock, flags); in cpm1_gpio16_dir_in()
473 clrbits16(&iop->dir, pin_mask); in cpm1_gpio16_dir_in()
475 spin_unlock_irqrestore(&cpm1_gc->lock, flags); in cpm1_gpio16_dir_in()
482 struct device_node *np = dev->of_node; in cpm1_gpiochip_add16()
490 return -ENOMEM; in cpm1_gpiochip_add16()
492 spin_lock_init(&cpm1_gc->lock); in cpm1_gpiochip_add16()
494 if (!of_property_read_u16(np, "fsl,cpm1-gpio-irq-mask", &mask)) { in cpm1_gpiochip_add16()
498 if (mask & (1 << (15 - i))) in cpm1_gpiochip_add16()
499 cpm1_gc->irq[i] = irq_of_parse_and_map(np, j++); in cpm1_gpiochip_add16()
502 mm_gc = &cpm1_gc->mm_gc; in cpm1_gpiochip_add16()
503 gc = &mm_gc->gc; in cpm1_gpiochip_add16()
505 mm_gc->save_regs = cpm1_gpio16_save_regs; in cpm1_gpiochip_add16()
506 gc->ngpio = 16; in cpm1_gpiochip_add16()
507 gc->direction_input = cpm1_gpio16_dir_in; in cpm1_gpiochip_add16()
508 gc->direction_output = cpm1_gpio16_dir_out; in cpm1_gpiochip_add16()
509 gc->get = cpm1_gpio16_get; in cpm1_gpiochip_add16()
510 gc->set = cpm1_gpio16_set; in cpm1_gpiochip_add16()
511 gc->to_irq = cpm1_gpio16_to_irq; in cpm1_gpiochip_add16()
512 gc->parent = dev; in cpm1_gpiochip_add16()
513 gc->owner = THIS_MODULE; in cpm1_gpiochip_add16()
530 struct cpm_ioport32b __iomem *iop = mm_gc->regs; in cpm1_gpio32_save_regs()
532 cpm1_gc->cpdata = in_be32(&iop->dat); in cpm1_gpio32_save_regs()
535 static int cpm1_gpio32_get(struct gpio_chip *gc, unsigned int gpio) in cpm1_gpio32_get() argument
538 struct cpm_ioport32b __iomem *iop = mm_gc->regs; in cpm1_gpio32_get()
541 pin_mask = 1 << (31 - gpio); in cpm1_gpio32_get()
543 return !!(in_be32(&iop->dat) & pin_mask); in cpm1_gpio32_get()
549 struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc); in __cpm1_gpio32_set()
550 struct cpm_ioport32b __iomem *iop = mm_gc->regs; in __cpm1_gpio32_set()
553 cpm1_gc->cpdata |= pin_mask; in __cpm1_gpio32_set()
555 cpm1_gc->cpdata &= ~pin_mask; in __cpm1_gpio32_set()
557 out_be32(&iop->dat, cpm1_gc->cpdata); in __cpm1_gpio32_set()
560 static void cpm1_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value) in cpm1_gpio32_set() argument
563 struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc); in cpm1_gpio32_set()
565 u32 pin_mask = 1 << (31 - gpio); in cpm1_gpio32_set()
567 spin_lock_irqsave(&cpm1_gc->lock, flags); in cpm1_gpio32_set()
571 spin_unlock_irqrestore(&cpm1_gc->lock, flags); in cpm1_gpio32_set()
574 static int cpm1_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) in cpm1_gpio32_dir_out() argument
577 struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc); in cpm1_gpio32_dir_out()
578 struct cpm_ioport32b __iomem *iop = mm_gc->regs; in cpm1_gpio32_dir_out()
580 u32 pin_mask = 1 << (31 - gpio); in cpm1_gpio32_dir_out()
582 spin_lock_irqsave(&cpm1_gc->lock, flags); in cpm1_gpio32_dir_out()
584 setbits32(&iop->dir, pin_mask); in cpm1_gpio32_dir_out()
587 spin_unlock_irqrestore(&cpm1_gc->lock, flags); in cpm1_gpio32_dir_out()
592 static int cpm1_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio) in cpm1_gpio32_dir_in() argument
595 struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc); in cpm1_gpio32_dir_in()
596 struct cpm_ioport32b __iomem *iop = mm_gc->regs; in cpm1_gpio32_dir_in()
598 u32 pin_mask = 1 << (31 - gpio); in cpm1_gpio32_dir_in()
600 spin_lock_irqsave(&cpm1_gc->lock, flags); in cpm1_gpio32_dir_in()
602 clrbits32(&iop->dir, pin_mask); in cpm1_gpio32_dir_in()
604 spin_unlock_irqrestore(&cpm1_gc->lock, flags); in cpm1_gpio32_dir_in()
611 struct device_node *np = dev->of_node; in cpm1_gpiochip_add32()
618 return -ENOMEM; in cpm1_gpiochip_add32()
620 spin_lock_init(&cpm1_gc->lock); in cpm1_gpiochip_add32()
622 mm_gc = &cpm1_gc->mm_gc; in cpm1_gpiochip_add32()
623 gc = &mm_gc->gc; in cpm1_gpiochip_add32()
625 mm_gc->save_regs = cpm1_gpio32_save_regs; in cpm1_gpiochip_add32()
626 gc->ngpio = 32; in cpm1_gpiochip_add32()
627 gc->direction_input = cpm1_gpio32_dir_in; in cpm1_gpiochip_add32()
628 gc->direction_output = cpm1_gpio32_dir_out; in cpm1_gpiochip_add32()
629 gc->get = cpm1_gpio32_get; in cpm1_gpiochip_add32()
630 gc->set = cpm1_gpio32_set; in cpm1_gpiochip_add32()
631 gc->parent = dev; in cpm1_gpiochip_add32()
632 gc->owner = THIS_MODULE; in cpm1_gpiochip_add32()