Lines Matching +full:irqs +full:- +full:map +full:- +full:range
23 * -----------------
26 * group has 3 irqs, External IRQ0, slice timer 0 irq, and wake from deep
27 * sleep. Main group include the other 3 external IRQs, slice timer 1, RTC,
29 * remaining irq sources from all of the on-chip peripherals (PSCs, Ethernet,
33 * -----
39 * a unique range of the global IRQ# space.
41 * To define a range of virq numbers for this controller, this driver first
61 * -------------------
62 * For actually manipulating IRQs (masking, enabling, clearing, etc) this
74 * register even though one of the external IRQs is in the critical group and
76 * the 4 external irqs to be managed using a separate set of hooks. The
77 * reason there is no crit irq_chip is that of the 3 irqs in the critical
83 * --------------------
85 * organization of irqs in the device. #interrupt-cells = <3> where the
90 * it is non-obvious to determine what the interrupts property should be
124 { .compatible = "fsl,mpc5200-pic", },
125 { .compatible = "mpc5200-pic", },
129 { .compatible = "fsl,mpc5200-bestcomm", },
130 { .compatible = "mpc5200-bestcomm", },
157 * IRQ[0-3] interrupt irq_chip
162 io_be_clrbit(&intr->ctrl, 11 - l2irq); in mpc52xx_extirq_mask()
168 io_be_setbit(&intr->ctrl, 11 - l2irq); in mpc52xx_extirq_unmask()
174 io_be_setbit(&intr->ctrl, 27-l2irq); in mpc52xx_extirq_ack()
195 ctrl_reg = in_be32(&intr->ctrl); in mpc52xx_extirq_set_type()
196 ctrl_reg &= ~(0x3 << (22 - (l2irq * 2))); in mpc52xx_extirq_set_type()
197 ctrl_reg |= (type << (22 - (l2irq * 2))); in mpc52xx_extirq_set_type()
198 out_be32(&intr->ctrl, ctrl_reg); in mpc52xx_extirq_set_type()
224 io_be_setbit(&intr->main_mask, 16 - l2irq); in mpc52xx_main_mask()
230 io_be_clrbit(&intr->main_mask, 16 - l2irq); in mpc52xx_main_unmask()
247 io_be_setbit(&intr->per_mask, 31 - l2irq); in mpc52xx_periph_mask()
253 io_be_clrbit(&intr->per_mask, 31 - l2irq); in mpc52xx_periph_unmask()
270 io_be_setbit(&sdma->IntMask, l2irq); in mpc52xx_sdma_mask()
276 io_be_clrbit(&sdma->IntMask, l2irq); in mpc52xx_sdma_unmask()
282 out_be32(&sdma->IntPend, 1 << l2irq); in mpc52xx_sdma_ack()
294 * mpc52xx_is_extirq - Returns true if hwirq number is for an external IRQ
303 * mpc52xx_irqhost_xlate - translate virq# from device tree interrupts property
316 return -1; in mpc52xx_irqhost_xlate()
337 * mpc52xx_irqhost_map - Hook to map from virq to an irq_chip structure
353 * External IRQs are handled differently by the hardware so they are in mpc52xx_irqhost_map()
357 reg = in_be32(&intr->ctrl); in mpc52xx_irqhost_map()
358 type = mpc52xx_map_senses[(reg >> (22 - l2irq * 2)) & 0x3]; in mpc52xx_irqhost_map()
391 .map = mpc52xx_irqhost_map,
395 * mpc52xx_init_irq - Initialize and register with the virq subsystem
397 * Hook for setting up IRQs on an mpc5200 system. A pointer to this function
413 panic(__FILE__ ": find_and_map failed on 'mpc5200-pic'. " in mpc52xx_init_irq()
420 panic(__FILE__ ": find_and_map failed on 'mpc5200-bestcomm'. " in mpc52xx_init_irq()
426 out_be32(&sdma->IntPend, 0xffffffff); /* 1 means clear pending */ in mpc52xx_init_irq()
427 out_be32(&sdma->IntMask, 0xffffffff); /* 1 means disabled */ in mpc52xx_init_irq()
428 out_be32(&intr->per_mask, 0x7ffffc00); /* 1 means disabled */ in mpc52xx_init_irq()
429 out_be32(&intr->main_mask, 0x00010fff); /* 1 means disabled */ in mpc52xx_init_irq()
430 intr_ctrl = in_be32(&intr->ctrl); in mpc52xx_init_irq()
431 intr_ctrl &= 0x00ff0000; /* Keeps IRQ[0-3] config */ in mpc52xx_init_irq()
432 intr_ctrl |= 0x0f000000 | /* clear IRQ 0-3 */ in mpc52xx_init_irq()
434 0x00000000 | /* 0 means disable IRQ 0-3 */ in mpc52xx_init_irq()
436 out_be32(&intr->ctrl, intr_ctrl); in mpc52xx_init_irq()
439 out_be32(&intr->per_pri1, 0); in mpc52xx_init_irq()
440 out_be32(&intr->per_pri2, 0); in mpc52xx_init_irq()
441 out_be32(&intr->per_pri3, 0); in mpc52xx_init_irq()
442 out_be32(&intr->main_pri1, 0); in mpc52xx_init_irq()
443 out_be32(&intr->main_pri2, 0); in mpc52xx_init_irq()
462 * mpc52xx_get_irq - Get pending interrupt number hook function
469 * types of interrupts defined by the controller - 'critical', 'main' and
485 * occurs at task-specific IRQ# is decoded so that each task can have its
493 status = in_be32(&intr->enc_status); in mpc52xx_get_irq()
508 status = in_be32(&sdma->IntPend); in mpc52xx_get_irq()
509 irq = ffs(status) - 1; in mpc52xx_get_irq()