642 	dcr_host_t		dcrs;  member
896 	dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x68782800);  in ppc440speA_pciex_init_utl()
1023 	dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0);  in ppc460ex_pciex_init_utl()
1362 	dcr_write(port->dcrs, DCRO_PEGPL_CFGBAH,  in ppc4xx_pciex_port_init_mapping()
1364 	dcr_write(port->dcrs, DCRO_PEGPL_CFGBAL,  in ppc4xx_pciex_port_init_mapping()
1368 	dcr_write(port->dcrs, DCRO_PEGPL_CFGMSK, 0xe0000001);  in ppc4xx_pciex_port_init_mapping()
1371 	dcr_write(port->dcrs, DCRO_PEGPL_REGBAH,  in ppc4xx_pciex_port_init_mapping()
1373 	dcr_write(port->dcrs, DCRO_PEGPL_REGBAL,  in ppc4xx_pciex_port_init_mapping()
1377 	dcr_write(port->dcrs, DCRO_PEGPL_REGMSK, 0x00007001);  in ppc4xx_pciex_port_init_mapping()
1380 	dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, 0);  in ppc4xx_pciex_port_init_mapping()
1381 	dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, 0);  in ppc4xx_pciex_port_init_mapping()
1382 	dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, 0);  in ppc4xx_pciex_port_init_mapping()
1383 	dcr_write(port->dcrs, DCRO_PEGPL_MSGMSK, 0);  in ppc4xx_pciex_port_init_mapping()
1520 	gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG);  in ppc4xx_pciex_read_config()
1521 	dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA);  in ppc4xx_pciex_read_config()
1551 	dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg);  in ppc4xx_pciex_read_config()
1575 	gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG);  in ppc4xx_pciex_write_config()
1576 	dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA);  in ppc4xx_pciex_write_config()
1595 	dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg);  in ppc4xx_pciex_write_config()
1637 		dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAH, lah);  in ppc4xx_setup_one_pciex_POM()
1638 		dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAL, lal);  in ppc4xx_setup_one_pciex_POM()
1639 		dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKH, 0x7fffffff);  in ppc4xx_setup_one_pciex_POM()
1642 			dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL,  in ppc4xx_setup_one_pciex_POM()
1649 			dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL,  in ppc4xx_setup_one_pciex_POM()
1653 			dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL,  in ppc4xx_setup_one_pciex_POM()
1660 		dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAH, lah);  in ppc4xx_setup_one_pciex_POM()
1661 		dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAL, lal);  in ppc4xx_setup_one_pciex_POM()
1662 		dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKH, 0x7fffffff);  in ppc4xx_setup_one_pciex_POM()
1663 		dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL,  in ppc4xx_setup_one_pciex_POM()
1669 		dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAH, lah);  in ppc4xx_setup_one_pciex_POM()
1670 		dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAL, lal);  in ppc4xx_setup_one_pciex_POM()
1671 		dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKH, 0x7fffffff);  in ppc4xx_setup_one_pciex_POM()
1673 		dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL,  in ppc4xx_setup_one_pciex_POM()
1977 	unsigned int dcrs;  in ppc4xx_probe_pciex_bridge()  local
2045 	dcrs = dcr_resource_start(np, 0);  in ppc4xx_probe_pciex_bridge()
2046 	if (dcrs == 0) {  in ppc4xx_probe_pciex_bridge()
2050 	port->dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0));  in ppc4xx_probe_pciex_bridge()