Lines Matching +full:max +full:- +full:outbound +full:- +full:regions
2 * PCI / PCI-X / PCI-Express support for 4xx parts
30 #include <asm/pci-bridge.h>
33 #include <asm/dcr-regs.h>
62 if (dev->devfn != 0 || dev->bus->self != NULL) in fixup_ppc4xx_pci_bridge()
65 hose = pci_bus_to_host(dev->bus); in fixup_ppc4xx_pci_bridge()
69 if (!of_device_is_compatible(hose->dn, "ibm,plb-pciex") && in fixup_ppc4xx_pci_bridge()
70 !of_device_is_compatible(hose->dn, "ibm,plb-pcix") && in fixup_ppc4xx_pci_bridge()
71 !of_device_is_compatible(hose->dn, "ibm,plb-pci")) in fixup_ppc4xx_pci_bridge()
74 if (of_device_is_compatible(hose->dn, "ibm,plb440epx-pci") || in fixup_ppc4xx_pci_bridge()
75 of_device_is_compatible(hose->dn, "ibm,plb440grx-pci")) { in fixup_ppc4xx_pci_bridge()
76 hose->indirect_type |= PPC_INDIRECT_TYPE_BROKEN_MRM; in fixup_ppc4xx_pci_bridge()
83 r->start = r->end = 0; in fixup_ppc4xx_pci_bridge()
84 r->flags = 0; in fixup_ppc4xx_pci_bridge()
99 int pna = of_n_addr_cells(hose->dn); in ppc4xx_parse_dma_ranges()
103 res->start = 0; in ppc4xx_parse_dma_ranges()
105 res->end = size - 1; in ppc4xx_parse_dma_ranges()
106 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; in ppc4xx_parse_dma_ranges()
108 /* Get dma-ranges property */ in ppc4xx_parse_dma_ranges()
109 ranges = of_get_property(hose->dn, "dma-ranges", &rlen); in ppc4xx_parse_dma_ranges()
114 while ((rlen -= np * 4) >= 0) { in ppc4xx_parse_dma_ranges()
117 u64 cpu_addr = of_translate_dma_address(hose->dn, ranges + 3); in ppc4xx_parse_dma_ranges()
132 " 0x%016llx...0x%016llx -> 0x%016llx\n", in ppc4xx_parse_dma_ranges()
133 hose->dn, in ppc4xx_parse_dma_ranges()
134 pci_addr, pci_addr + size - 1, cpu_addr); in ppc4xx_parse_dma_ranges()
140 res->flags &= ~IORESOURCE_PREFETCH; in ppc4xx_parse_dma_ranges()
144 res->start = pci_addr; in ppc4xx_parse_dma_ranges()
148 res->end = 0xffffffff; in ppc4xx_parse_dma_ranges()
150 res->end = res->start + size - 1; in ppc4xx_parse_dma_ranges()
155 if (dma_offset_set && pci_dram_offset != res->start) { in ppc4xx_parse_dma_ranges()
156 printk(KERN_ERR "%pOF: dma-ranges(s) mismatch\n", hose->dn); in ppc4xx_parse_dma_ranges()
157 return -ENXIO; in ppc4xx_parse_dma_ranges()
164 printk(KERN_ERR "%pOF: dma-ranges too small " in ppc4xx_parse_dma_ranges()
166 hose->dn, size, (u64)total_memory); in ppc4xx_parse_dma_ranges()
167 return -ENXIO; in ppc4xx_parse_dma_ranges()
171 if ((size & (size - 1)) != 0 || in ppc4xx_parse_dma_ranges()
172 (res->start & (size - 1)) != 0) { in ppc4xx_parse_dma_ranges()
173 printk(KERN_ERR "%pOF: dma-ranges unaligned\n", hose->dn); in ppc4xx_parse_dma_ranges()
174 return -ENXIO; in ppc4xx_parse_dma_ranges()
180 if (res->end > 0xffffffff && in ppc4xx_parse_dma_ranges()
181 !(of_device_is_compatible(hose->dn, "ibm,plb-pciex-460sx") in ppc4xx_parse_dma_ranges()
182 || of_device_is_compatible(hose->dn, "ibm,plb-pciex-476fpe"))) { in ppc4xx_parse_dma_ranges()
183 printk(KERN_ERR "%pOF: dma-ranges outside of 32 bits space\n", in ppc4xx_parse_dma_ranges()
184 hose->dn); in ppc4xx_parse_dma_ranges()
185 return -ENXIO; in ppc4xx_parse_dma_ranges()
189 pci_dram_offset = res->start; in ppc4xx_parse_dma_ranges()
190 hose->dma_window_base_cur = res->start; in ppc4xx_parse_dma_ranges()
191 hose->dma_window_size = resource_size(res); in ppc4xx_parse_dma_ranges()
196 (unsigned long long)hose->dma_window_base_cur); in ppc4xx_parse_dma_ranges()
198 (unsigned long long)hose->dma_window_size); in ppc4xx_parse_dma_ranges()
217 * 32-bit of incoming PLB addresses. The top 4 bits of the 36-bit in ppc4xx_setup_one_pci_PMM()
222 * programming the chip. That means the device-tree has to be right in ppc4xx_setup_one_pci_PMM()
234 size < 0x1000 || (plb_addr & (size - 1)) != 0) { in ppc4xx_setup_one_pci_PMM()
235 printk(KERN_WARNING "%pOF: Resource out of range\n", hose->dn); in ppc4xx_setup_one_pci_PMM()
236 return -1; in ppc4xx_setup_one_pci_PMM()
258 /* Setup outbound memory windows */ in ppc4xx_configure_pci_PMMs()
260 struct resource *res = &hose->mem_resources[i]; in ppc4xx_configure_pci_PMMs()
261 resource_size_t offset = hose->mem_offset[i]; in ppc4xx_configure_pci_PMMs()
264 if (!(res->flags & IORESOURCE_MEM)) in ppc4xx_configure_pci_PMMs()
267 printk(KERN_WARNING "%pOF: Too many ranges\n", hose->dn); in ppc4xx_configure_pci_PMMs()
273 res->start, in ppc4xx_configure_pci_PMMs()
274 res->start - offset, in ppc4xx_configure_pci_PMMs()
276 res->flags, in ppc4xx_configure_pci_PMMs()
283 if (res->start == offset) in ppc4xx_configure_pci_PMMs()
289 if (j <= 2 && !found_isa_hole && hose->isa_mem_size) in ppc4xx_configure_pci_PMMs()
290 if (ppc4xx_setup_one_pci_PMM(hose, reg, hose->isa_mem_phys, 0, in ppc4xx_configure_pci_PMMs()
291 hose->isa_mem_size, 0, j) == 0) in ppc4xx_configure_pci_PMMs()
293 hose->dn); in ppc4xx_configure_pci_PMMs()
312 early_write_config_dword(hose, hose->first_busno, 0, in ppc4xx_configure_pci_PTMs()
313 PCI_BASE_ADDRESS_1, res->start); in ppc4xx_configure_pci_PTMs()
314 early_write_config_dword(hose, hose->first_busno, 0, in ppc4xx_configure_pci_PTMs()
316 early_write_config_word(hose, hose->first_busno, 0, in ppc4xx_configure_pci_PTMs()
333 printk(KERN_INFO "%pOF: Port disabled via device-tree\n", np); in ppc4xx_probe_pci_bridge()
355 bus_range = of_get_property(np, "bus-range", NULL); in ppc4xx_probe_pci_bridge()
369 hose->first_busno = bus_range ? bus_range[0] : 0x0; in ppc4xx_probe_pci_bridge()
370 hose->last_busno = bus_range ? bus_range[1] : 0xff; in ppc4xx_probe_pci_bridge()
382 /* Parse outbound mapping resources */ in ppc4xx_probe_pci_bridge()
389 /* Configure outbound ranges POMs */ in ppc4xx_probe_pci_bridge()
407 * 4xx PCI-X part
421 (plb_addr & (size - 1)) != 0) { in ppc4xx_setup_one_pcix_POM()
423 hose->dn); in ppc4xx_setup_one_pcix_POM()
424 return -1; in ppc4xx_setup_one_pcix_POM()
457 /* Setup outbound memory windows */ in ppc4xx_configure_pcix_POMs()
459 struct resource *res = &hose->mem_resources[i]; in ppc4xx_configure_pcix_POMs()
460 resource_size_t offset = hose->mem_offset[i]; in ppc4xx_configure_pcix_POMs()
463 if (!(res->flags & IORESOURCE_MEM)) in ppc4xx_configure_pcix_POMs()
466 printk(KERN_WARNING "%pOF: Too many ranges\n", hose->dn); in ppc4xx_configure_pcix_POMs()
472 res->start, in ppc4xx_configure_pcix_POMs()
473 res->start - offset, in ppc4xx_configure_pcix_POMs()
475 res->flags, in ppc4xx_configure_pcix_POMs()
482 if (res->start == offset) in ppc4xx_configure_pcix_POMs()
488 if (j <= 1 && !found_isa_hole && hose->isa_mem_size) in ppc4xx_configure_pcix_POMs()
489 if (ppc4xx_setup_one_pcix_POM(hose, reg, hose->isa_mem_phys, 0, in ppc4xx_configure_pcix_POMs()
490 hose->isa_mem_size, 0, j) == 0) in ppc4xx_configure_pcix_POMs()
492 hose->dn); in ppc4xx_configure_pcix_POMs()
511 if (res->flags & IORESOURCE_PREFETCH) in ppc4xx_configure_pcix_PIMs()
521 writel(res->start, reg + PCIX0_BAR0L); in ppc4xx_configure_pcix_PIMs()
537 printk(KERN_ERR "%pOF: Can't get PCI-X config register base !", in ppc4xx_probe_pcix_bridge()
543 printk(KERN_ERR "%pOF: Can't get PCI-X internal register base !", in ppc4xx_probe_pcix_bridge()
549 big_pim = of_property_read_bool(np, "large-inbound-windows"); in ppc4xx_probe_pcix_bridge()
552 msi = of_property_read_bool(np, "enable-msi-hole"); in ppc4xx_probe_pcix_bridge()
558 bus_range = of_get_property(np, "bus-range", NULL); in ppc4xx_probe_pcix_bridge()
572 hose->first_busno = bus_range ? bus_range[0] : 0x0; in ppc4xx_probe_pcix_bridge()
573 hose->last_busno = bus_range ? bus_range[1] : 0xff; in ppc4xx_probe_pcix_bridge()
591 /* Parse outbound mapping resources */ in ppc4xx_probe_pcix_bridge()
598 /* Configure outbound ranges POMs */ in ppc4xx_probe_pcix_bridge()
618 * 4xx PCI-Express part
622 * ibm,plb-pciex-440spe
623 * ibm,plb-pciex-405ex
624 * ibm,plb-pciex-460ex
670 while(timeout_ms--) { in ppc4xx_pciex_wait_on_sdr()
671 val = mfdcri(SDR0, port->sdr_base + sdr_offset); in ppc4xx_pciex_wait_on_sdr()
674 port->index, sdr_offset, timeout_ms, val); in ppc4xx_pciex_wait_on_sdr()
679 return -1; in ppc4xx_pciex_wait_on_sdr()
687 port->index); in ppc4xx_pciex_port_reset_sdr()
688 return -1; in ppc4xx_pciex_port_reset_sdr()
696 printk(KERN_INFO "PCIE%d: Checking link...\n", port->index); in ppc4xx_pciex_check_link_sdr()
705 if (!port->has_ibpre || in ppc4xx_pciex_check_link_sdr()
710 port->index); in ppc4xx_pciex_check_link_sdr()
714 "PCIE%d: Link up failed\n", port->index); in ppc4xx_pciex_check_link_sdr()
717 "PCIE%d: link is up !\n", port->index); in ppc4xx_pciex_check_link_sdr()
718 port->link = 1; in ppc4xx_pciex_check_link_sdr()
721 printk(KERN_INFO "PCIE%d: No device detected.\n", port->index); in ppc4xx_pciex_check_link_sdr()
736 * by firmware - let's re-reset RCSSET regs in ppc440spe_pciex_check_reset()
738 * -- Shouldn't we also re-reset the whole thing ? -- BenH in ppc440spe_pciex_check_reset()
755 err = -1; in ppc440spe_pciex_check_reset()
763 err = -1; in ppc440spe_pciex_check_reset()
771 err = -1; in ppc440spe_pciex_check_reset()
779 err = -1; in ppc440spe_pciex_check_reset()
787 err = -1; in ppc440spe_pciex_check_reset()
795 err = -1; in ppc440spe_pciex_check_reset()
811 return -ENXIO; in ppc440spe_pciex_core_init()
817 return -1; in ppc440spe_pciex_core_init()
820 /* De-assert reset of PCIe PLL, wait for lock */ in ppc440spe_pciex_core_init()
826 time_out--; in ppc440spe_pciex_core_init()
833 return -1; in ppc440spe_pciex_core_init()
845 if (port->endpoint) in ppc440spe_pciex_init_port_hw()
850 if (port->index == 0) in ppc440spe_pciex_init_port_hw()
855 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val); in ppc440spe_pciex_init_port_hw()
856 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x20222222); in ppc440spe_pciex_init_port_hw()
858 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x11000000); in ppc440spe_pciex_init_port_hw()
859 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL0SET1, 0x35000000); in ppc440spe_pciex_init_port_hw()
860 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL1SET1, 0x35000000); in ppc440spe_pciex_init_port_hw()
861 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL2SET1, 0x35000000); in ppc440spe_pciex_init_port_hw()
862 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL3SET1, 0x35000000); in ppc440spe_pciex_init_port_hw()
863 if (port->index == 0) { in ppc440spe_pciex_init_port_hw()
864 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL4SET1, in ppc440spe_pciex_init_port_hw()
866 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL5SET1, in ppc440spe_pciex_init_port_hw()
868 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL6SET1, in ppc440spe_pciex_init_port_hw()
870 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL7SET1, in ppc440spe_pciex_init_port_hw()
873 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, in ppc440spe_pciex_init_port_hw()
888 port->has_ibpre = 1; in ppc440speB_pciex_init_port_hw()
896 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x68782800); in ppc440speA_pciex_init_utl()
901 out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000); in ppc440speA_pciex_init_utl()
902 out_be32(port->utl_base + PEUTL_INTR, 0x02000000); in ppc440speA_pciex_init_utl()
903 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x10000000); in ppc440speA_pciex_init_utl()
904 out_be32(port->utl_base + PEUTL_PBBSZ, 0x53000000); in ppc440speA_pciex_init_utl()
905 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x08000000); in ppc440speA_pciex_init_utl()
906 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x10000000); in ppc440speA_pciex_init_utl()
907 out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000); in ppc440speA_pciex_init_utl()
908 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066); in ppc440speA_pciex_init_utl()
916 out_be32(port->utl_base + PEUTL_PBCTL, 0x08000000); in ppc440speB_pciex_init_utl()
950 if (port->endpoint) in ppc460ex_pciex_init_port_hw()
955 if (port->index == 0) { in ppc460ex_pciex_init_port_hw()
963 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val); in ppc460ex_pciex_init_port_hw()
964 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, utlset1); in ppc460ex_pciex_init_port_hw()
965 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01210000); in ppc460ex_pciex_init_port_hw()
967 switch (port->index) { in ppc460ex_pciex_init_port_hw()
994 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, in ppc460ex_pciex_init_port_hw()
995 mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) | in ppc460ex_pciex_init_port_hw()
1000 switch (port->index) { in ppc460ex_pciex_init_port_hw()
1011 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, in ppc460ex_pciex_init_port_hw()
1012 (mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) & in ppc460ex_pciex_init_port_hw()
1016 port->has_ibpre = 1; in ppc460ex_pciex_init_port_hw()
1023 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0); in ppc460ex_pciex_init_utl()
1028 out_be32(port->utl_base + PEUTL_PBCTL, 0x0800000c); in ppc460ex_pciex_init_utl()
1029 out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000); in ppc460ex_pciex_init_utl()
1030 out_be32(port->utl_base + PEUTL_INTR, 0x02000000); in ppc460ex_pciex_init_utl()
1031 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000); in ppc460ex_pciex_init_utl()
1032 out_be32(port->utl_base + PEUTL_PBBSZ, 0x00000000); in ppc460ex_pciex_init_utl()
1033 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000); in ppc460ex_pciex_init_utl()
1034 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000); in ppc460ex_pciex_init_utl()
1035 out_be32(port->utl_base + PEUTL_RCIRQEN,0x00f00000); in ppc460ex_pciex_init_utl()
1036 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066); in ppc460ex_pciex_init_utl()
1062 * This code is to fix the issue that pci drivers doesn't re-assign in apm821xx_pciex_init_port_hw()
1071 if (port->endpoint) in apm821xx_pciex_init_port_hw()
1078 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val); in apm821xx_pciex_init_port_hw()
1079 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000); in apm821xx_pciex_init_port_hw()
1080 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000); in apm821xx_pciex_init_port_hw()
1090 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, in apm821xx_pciex_init_port_hw()
1091 mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) | in apm821xx_pciex_init_port_hw()
1095 val = PESDR0_460EX_RSTSTA - port->sdr_base; in apm821xx_pciex_init_port_hw()
1098 return -EBUSY; in apm821xx_pciex_init_port_hw()
1100 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, in apm821xx_pciex_init_port_hw()
1101 (mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) & in apm821xx_pciex_init_port_hw()
1105 port->has_ibpre = 1; in apm821xx_pciex_init_port_hw()
1140 /* HSS TX pre-emphasis */ in ppc460sx_pciex_core_init()
1176 /* De-assert PLLRESET */ in ppc460sx_pciex_core_init()
1190 * If bifurcation is not enabled, u-boot would have disabled the in ppc460sx_pciex_core_init()
1207 if (port->endpoint) in ppc460sx_pciex_init_port_hw()
1208 dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2, in ppc460sx_pciex_init_port_hw()
1211 dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2, in ppc460sx_pciex_init_port_hw()
1214 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, in ppc460sx_pciex_init_port_hw()
1218 port->has_ibpre = 1; in ppc460sx_pciex_init_port_hw()
1225 /* Max 128 Bytes */ in ppc460sx_pciex_init_utl()
1226 out_be32 (port->utl_base + PEUTL_PBBSZ, 0x00000000); in ppc460sx_pciex_init_utl()
1227 /* Assert VRB and TXE - per datasheet turn off addr validation */ in ppc460sx_pciex_init_utl()
1228 out_be32(port->utl_base + PEUTL_PCTL, 0x80800000); in ppc460sx_pciex_init_utl()
1237 port->link = 0; in ppc460sx_pciex_check_link()
1239 mbase = ioremap(port->cfg_space.start + 0x10000000, 0x1000); in ppc460sx_pciex_check_link()
1242 port->node); in ppc460sx_pciex_check_link()
1248 attempt--; in ppc460sx_pciex_check_link()
1252 port->link = 1; in ppc460sx_pciex_check_link()
1276 void __iomem *mbase = ioremap(port->cfg_space.start + 0x10000000, in ppc_476fpe_pciex_check_link()
1279 printk(KERN_INFO "PCIE%d: Checking link...\n", port->index); in ppc_476fpe_pciex_check_link()
1283 port->index); in ppc_476fpe_pciex_check_link()
1287 while (timeout_ms--) { in ppc_476fpe_pciex_check_link()
1296 printk(KERN_INFO "PCIE%d: link is up !\n", port->index); in ppc_476fpe_pciex_check_link()
1297 port->link = 1; in ppc_476fpe_pciex_check_link()
1299 printk(KERN_WARNING "PCIE%d: Link up failed\n", port->index); in ppc_476fpe_pciex_check_link()
1315 int count = -ENODEV; in ppc4xx_pciex_check_core_init()
1321 if (of_device_is_compatible(np, "ibm,plb-pciex-440spe")) { in ppc4xx_pciex_check_core_init()
1327 if (of_device_is_compatible(np, "ibm,plb-pciex-460ex")) in ppc4xx_pciex_check_core_init()
1329 if (of_device_is_compatible(np, "ibm,plb-pciex-460sx")) in ppc4xx_pciex_check_core_init()
1331 if (of_device_is_compatible(np, "ibm,plb-pciex-apm821xx")) in ppc4xx_pciex_check_core_init()
1335 if (of_device_is_compatible(np, "ibm,plb-pciex-476fpe") in ppc4xx_pciex_check_core_init()
1336 || of_device_is_compatible(np, "ibm,plb-pciex-476gtr")) in ppc4xx_pciex_check_core_init()
1341 return -ENODEV; in ppc4xx_pciex_check_core_init()
1344 count = ppc4xx_pciex_hwops->core_init(np); in ppc4xx_pciex_check_core_init()
1354 return -ENOMEM; in ppc4xx_pciex_check_core_init()
1356 return -ENODEV; in ppc4xx_pciex_check_core_init()
1362 dcr_write(port->dcrs, DCRO_PEGPL_CFGBAH, in ppc4xx_pciex_port_init_mapping()
1363 RES_TO_U32_HIGH(port->cfg_space.start)); in ppc4xx_pciex_port_init_mapping()
1364 dcr_write(port->dcrs, DCRO_PEGPL_CFGBAL, in ppc4xx_pciex_port_init_mapping()
1365 RES_TO_U32_LOW(port->cfg_space.start)); in ppc4xx_pciex_port_init_mapping()
1368 dcr_write(port->dcrs, DCRO_PEGPL_CFGMSK, 0xe0000001); in ppc4xx_pciex_port_init_mapping()
1371 dcr_write(port->dcrs, DCRO_PEGPL_REGBAH, in ppc4xx_pciex_port_init_mapping()
1372 RES_TO_U32_HIGH(port->utl_regs.start)); in ppc4xx_pciex_port_init_mapping()
1373 dcr_write(port->dcrs, DCRO_PEGPL_REGBAL, in ppc4xx_pciex_port_init_mapping()
1374 RES_TO_U32_LOW(port->utl_regs.start)); in ppc4xx_pciex_port_init_mapping()
1377 dcr_write(port->dcrs, DCRO_PEGPL_REGMSK, 0x00007001); in ppc4xx_pciex_port_init_mapping()
1379 /* Disable all other outbound windows */ in ppc4xx_pciex_port_init_mapping()
1380 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, 0); in ppc4xx_pciex_port_init_mapping()
1381 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, 0); in ppc4xx_pciex_port_init_mapping()
1382 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, 0); in ppc4xx_pciex_port_init_mapping()
1383 dcr_write(port->dcrs, DCRO_PEGPL_MSGMSK, 0); in ppc4xx_pciex_port_init_mapping()
1391 if (ppc4xx_pciex_hwops->port_init_hw) in ppc4xx_pciex_port_init()
1392 rc = ppc4xx_pciex_hwops->port_init_hw(port); in ppc4xx_pciex_port_init()
1397 * Initialize mapping: disable all regions and configure in ppc4xx_pciex_port_init()
1398 * CFG and REG regions based on resources in the device tree in ppc4xx_pciex_port_init()
1402 if (ppc4xx_pciex_hwops->check_link) in ppc4xx_pciex_port_init()
1403 ppc4xx_pciex_hwops->check_link(port); in ppc4xx_pciex_port_init()
1408 port->utl_base = ioremap(port->utl_regs.start, 0x100); in ppc4xx_pciex_port_init()
1409 BUG_ON(port->utl_base == NULL); in ppc4xx_pciex_port_init()
1412 * Setup UTL registers --BenH. in ppc4xx_pciex_port_init()
1414 if (ppc4xx_pciex_hwops->setup_utl) in ppc4xx_pciex_port_init()
1415 ppc4xx_pciex_hwops->setup_utl(port); in ppc4xx_pciex_port_init()
1420 if (port->sdr_base) { in ppc4xx_pciex_port_init()
1421 if (of_device_is_compatible(port->node, in ppc4xx_pciex_port_init()
1422 "ibm,plb-pciex-460sx")){ in ppc4xx_pciex_port_init()
1423 if (port->link && ppc4xx_pciex_wait_on_sdr(port, in ppc4xx_pciex_port_init()
1427 port->index); in ppc4xx_pciex_port_init()
1428 port->link = 0; in ppc4xx_pciex_port_init()
1430 } else if (port->link && in ppc4xx_pciex_port_init()
1434 port->index); in ppc4xx_pciex_port_init()
1435 port->link = 0; in ppc4xx_pciex_port_init()
1438 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20); in ppc4xx_pciex_port_init()
1453 if (port->endpoint && bus->number != port->hose->first_busno) in ppc4xx_pciex_validate_bdf()
1457 if (bus->number > port->hose->last_busno) { in ppc4xx_pciex_validate_bdf()
1460 " out of range !\n", bus->number); in ppc4xx_pciex_validate_bdf()
1467 if (bus->number == port->hose->first_busno && devfn != 0) in ppc4xx_pciex_validate_bdf()
1471 if (bus->number == (port->hose->first_busno + 1) && in ppc4xx_pciex_validate_bdf()
1476 if ((bus->number != port->hose->first_busno) && !port->link) in ppc4xx_pciex_validate_bdf()
1491 if (bus->number == port->hose->first_busno) in ppc4xx_pciex_get_config_base()
1492 return (void __iomem *)port->hose->cfg_addr; in ppc4xx_pciex_get_config_base()
1494 relbus = bus->number - (port->hose->first_busno + 1); in ppc4xx_pciex_get_config_base()
1495 return (void __iomem *)port->hose->cfg_data + in ppc4xx_pciex_get_config_base()
1504 &ppc4xx_pciex_ports[hose->indirect_type]; in ppc4xx_pciex_read_config()
1508 BUG_ON(hose != port->hose); in ppc4xx_pciex_read_config()
1516 * Reading from configuration space of non-existing device can in ppc4xx_pciex_read_config()
1520 gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG); in ppc4xx_pciex_read_config()
1521 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA); in ppc4xx_pciex_read_config()
1524 out_be32(port->utl_base + PEUTL_RCSTA, 0x00040000); in ppc4xx_pciex_read_config()
1538 pr_debug("pcie-config-read: bus=%3d [%3d..%3d] devfn=0x%04x" in ppc4xx_pciex_read_config()
1540 bus->number, hose->first_busno, hose->last_busno, in ppc4xx_pciex_read_config()
1544 if (in_be32(port->utl_base + PEUTL_RCSTA) & 0x00040000) { in ppc4xx_pciex_read_config()
1551 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg); in ppc4xx_pciex_read_config()
1561 &ppc4xx_pciex_ports[hose->indirect_type]; in ppc4xx_pciex_write_config()
1571 * Reading from configuration space of non-existing device can in ppc4xx_pciex_write_config()
1575 gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG); in ppc4xx_pciex_write_config()
1576 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA); in ppc4xx_pciex_write_config()
1578 pr_debug("pcie-config-write: bus=%3d [%3d..%3d] devfn=0x%04x" in ppc4xx_pciex_write_config()
1580 bus->number, hose->first_busno, hose->last_busno, in ppc4xx_pciex_write_config()
1595 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg); in ppc4xx_pciex_write_config()
1620 (plb_addr & (size - 1)) != 0) { in ppc4xx_setup_one_pciex_POM()
1621 printk(KERN_WARNING "%pOF: Resource out of range\n", hose->dn); in ppc4xx_setup_one_pciex_POM()
1622 return -1; in ppc4xx_setup_one_pciex_POM()
1637 dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAH, lah); in ppc4xx_setup_one_pciex_POM()
1638 dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAL, lal); in ppc4xx_setup_one_pciex_POM()
1639 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKH, 0x7fffffff); in ppc4xx_setup_one_pciex_POM()
1641 if (of_device_is_compatible(port->node, "ibm,plb-pciex-460sx")) in ppc4xx_setup_one_pciex_POM()
1642 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, in ppc4xx_setup_one_pciex_POM()
1646 port->node, "ibm,plb-pciex-476fpe") || in ppc4xx_setup_one_pciex_POM()
1648 port->node, "ibm,plb-pciex-476gtr")) in ppc4xx_setup_one_pciex_POM()
1649 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, in ppc4xx_setup_one_pciex_POM()
1653 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, in ppc4xx_setup_one_pciex_POM()
1660 dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAH, lah); in ppc4xx_setup_one_pciex_POM()
1661 dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAL, lal); in ppc4xx_setup_one_pciex_POM()
1662 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKH, 0x7fffffff); in ppc4xx_setup_one_pciex_POM()
1663 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, in ppc4xx_setup_one_pciex_POM()
1669 dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAH, lah); in ppc4xx_setup_one_pciex_POM()
1670 dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAL, lal); in ppc4xx_setup_one_pciex_POM()
1671 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKH, 0x7fffffff); in ppc4xx_setup_one_pciex_POM()
1673 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, in ppc4xx_setup_one_pciex_POM()
1688 /* Setup outbound memory windows */ in ppc4xx_configure_pciex_POMs()
1690 struct resource *res = &hose->mem_resources[i]; in ppc4xx_configure_pciex_POMs()
1691 resource_size_t offset = hose->mem_offset[i]; in ppc4xx_configure_pciex_POMs()
1694 if (!(res->flags & IORESOURCE_MEM)) in ppc4xx_configure_pciex_POMs()
1698 port->node); in ppc4xx_configure_pciex_POMs()
1704 res->start, in ppc4xx_configure_pciex_POMs()
1705 res->start - offset, in ppc4xx_configure_pciex_POMs()
1707 res->flags, in ppc4xx_configure_pciex_POMs()
1714 if (res->start == offset) in ppc4xx_configure_pciex_POMs()
1720 if (j <= 1 && !found_isa_hole && hose->isa_mem_size) in ppc4xx_configure_pciex_POMs()
1722 hose->isa_mem_phys, 0, in ppc4xx_configure_pciex_POMs()
1723 hose->isa_mem_size, 0, j) == 0) in ppc4xx_configure_pciex_POMs()
1725 hose->dn); in ppc4xx_configure_pciex_POMs()
1728 * Note also that it -has- to be region index 2 on this HW in ppc4xx_configure_pciex_POMs()
1730 if (hose->io_resource.flags & IORESOURCE_IO) in ppc4xx_configure_pciex_POMs()
1732 hose->io_base_phys, 0, in ppc4xx_configure_pciex_POMs()
1744 if (port->endpoint) { in ppc4xx_configure_pciex_PIMs()
1774 if (res->flags & IORESOURCE_PREFETCH) in ppc4xx_configure_pciex_PIMs()
1777 if (of_device_is_compatible(port->node, "ibm,plb-pciex-460sx") || in ppc4xx_configure_pciex_PIMs()
1779 port->node, "ibm,plb-pciex-476fpe") || in ppc4xx_configure_pciex_PIMs()
1781 port->node, "ibm,plb-pciex-476gtr")) in ppc4xx_configure_pciex_PIMs()
1797 out_le32(mbase + PCI_BASE_ADDRESS_0, RES_TO_U32_LOW(res->start)); in ppc4xx_configure_pciex_PIMs()
1798 out_le32(mbase + PCI_BASE_ADDRESS_1, RES_TO_U32_HIGH(res->start)); in ppc4xx_configure_pciex_PIMs()
1821 primary = of_property_read_bool(port->node, "primary"); in ppc4xx_pciex_port_setup_hose()
1824 bus_range = of_get_property(port->node, "bus-range", NULL); in ppc4xx_pciex_port_setup_hose()
1827 hose = pcibios_alloc_controller(port->node); in ppc4xx_pciex_port_setup_hose()
1834 hose->indirect_type = port->index; in ppc4xx_pciex_port_setup_hose()
1837 hose->first_busno = bus_range ? bus_range[0] : 0x0; in ppc4xx_pciex_port_setup_hose()
1838 hose->last_busno = bus_range ? bus_range[1] : 0xff; in ppc4xx_pciex_port_setup_hose()
1845 busses = hose->last_busno - hose->first_busno; /* This is off by 1 */ in ppc4xx_pciex_port_setup_hose()
1848 hose->last_busno = hose->first_busno + busses; in ppc4xx_pciex_port_setup_hose()
1851 if (!port->endpoint) { in ppc4xx_pciex_port_setup_hose()
1853 * PCIe root-complexes. External space is 1M per bus in ppc4xx_pciex_port_setup_hose()
1855 cfg_data = ioremap(port->cfg_space.start + in ppc4xx_pciex_port_setup_hose()
1856 (hose->first_busno + 1) * 0x100000, in ppc4xx_pciex_port_setup_hose()
1860 port->node); in ppc4xx_pciex_port_setup_hose()
1863 hose->cfg_data = cfg_data; in ppc4xx_pciex_port_setup_hose()
1869 mbase = ioremap(port->cfg_space.start + 0x10000000, 0x1000); in ppc4xx_pciex_port_setup_hose()
1872 port->node); in ppc4xx_pciex_port_setup_hose()
1875 hose->cfg_addr = mbase; in ppc4xx_pciex_port_setup_hose()
1877 pr_debug("PCIE %pOF, bus %d..%d\n", port->node, in ppc4xx_pciex_port_setup_hose()
1878 hose->first_busno, hose->last_busno); in ppc4xx_pciex_port_setup_hose()
1880 hose->cfg_addr, hose->cfg_data); in ppc4xx_pciex_port_setup_hose()
1883 hose->ops = &ppc4xx_pciex_pci_ops; in ppc4xx_pciex_port_setup_hose()
1884 port->hose = hose; in ppc4xx_pciex_port_setup_hose()
1885 mbase = (void __iomem *)hose->cfg_addr; in ppc4xx_pciex_port_setup_hose()
1887 if (!port->endpoint) { in ppc4xx_pciex_port_setup_hose()
1891 out_8(mbase + PCI_PRIMARY_BUS, hose->first_busno); in ppc4xx_pciex_port_setup_hose()
1892 out_8(mbase + PCI_SECONDARY_BUS, hose->first_busno + 1); in ppc4xx_pciex_port_setup_hose()
1893 out_8(mbase + PCI_SUBORDINATE_BUS, hose->last_busno); in ppc4xx_pciex_port_setup_hose()
1901 /* Parse outbound mapping resources */ in ppc4xx_pciex_port_setup_hose()
1902 pci_process_bridge_OF_ranges(hose, port->node, primary); in ppc4xx_pciex_port_setup_hose()
1908 /* Configure outbound ranges POMs */ in ppc4xx_pciex_port_setup_hose()
1917 * overwritten by setting the "vendor-id/device-id" properties in ppc4xx_pciex_port_setup_hose()
1921 /* Get the (optional) vendor-/device-id from the device-tree */ in ppc4xx_pciex_port_setup_hose()
1922 pval = of_get_property(port->node, "vendor-id", NULL); in ppc4xx_pciex_port_setup_hose()
1926 if (!port->endpoint) in ppc4xx_pciex_port_setup_hose()
1927 val = 0xaaa0 + port->index; in ppc4xx_pciex_port_setup_hose()
1929 val = 0xeee0 + port->index; in ppc4xx_pciex_port_setup_hose()
1933 pval = of_get_property(port->node, "device-id", NULL); in ppc4xx_pciex_port_setup_hose()
1937 if (!port->endpoint) in ppc4xx_pciex_port_setup_hose()
1938 val = 0xbed0 + port->index; in ppc4xx_pciex_port_setup_hose()
1940 val = 0xfed0 + port->index; in ppc4xx_pciex_port_setup_hose()
1945 if (of_device_is_compatible(port->node, "ibm,plb-pciex-460sx")) in ppc4xx_pciex_port_setup_hose()
1948 if (!port->endpoint) { in ppc4xx_pciex_port_setup_hose()
1949 /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */ in ppc4xx_pciex_port_setup_hose()
1952 printk(KERN_INFO "PCIE%d: successfully set as root-complex\n", in ppc4xx_pciex_port_setup_hose()
1953 port->index); in ppc4xx_pciex_port_setup_hose()
1959 port->index); in ppc4xx_pciex_port_setup_hose()
1985 /* Get the port number from the device-tree */ in ppc4xx_probe_pciex_bridge()
1998 port->index = portno; in ppc4xx_probe_pciex_bridge()
2004 printk(KERN_INFO "PCIE%d: Port disabled via device-tree\n", port->index); in ppc4xx_probe_pciex_bridge()
2008 port->node = of_node_get(np); in ppc4xx_probe_pciex_bridge()
2009 if (ppc4xx_pciex_hwops->want_sdr) { in ppc4xx_probe_pciex_bridge()
2010 pval = of_get_property(np, "sdr-base", NULL); in ppc4xx_probe_pciex_bridge()
2012 printk(KERN_ERR "PCIE: missing sdr-base for %pOF\n", in ppc4xx_probe_pciex_bridge()
2016 port->sdr_base = *pval; in ppc4xx_probe_pciex_bridge()
2019 /* Check if device_type property is set to "pci" or "pci-endpoint". in ppc4xx_probe_pciex_bridge()
2021 * as root-complex or as endpoint. in ppc4xx_probe_pciex_bridge()
2023 if (of_node_is_type(port->node, "pci-endpoint")) { in ppc4xx_probe_pciex_bridge()
2024 port->endpoint = 1; in ppc4xx_probe_pciex_bridge()
2025 } else if (of_node_is_type(port->node, "pci")) { in ppc4xx_probe_pciex_bridge()
2026 port->endpoint = 0; in ppc4xx_probe_pciex_bridge()
2034 if (of_address_to_resource(np, 0, &port->cfg_space)) { in ppc4xx_probe_pciex_bridge()
2035 printk(KERN_ERR "%pOF: Can't get PCI-E config space !", np); in ppc4xx_probe_pciex_bridge()
2039 if (of_address_to_resource(np, 1, &port->utl_regs)) { in ppc4xx_probe_pciex_bridge()
2050 port->dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0)); in ppc4xx_probe_pciex_bridge()
2054 printk(KERN_WARNING "PCIE%d: Port init failed\n", port->index); in ppc4xx_probe_pciex_bridge()
2071 for_each_compatible_node(np, NULL, "ibm,plb-pciex") in ppc4xx_pci_find_bridges()
2074 for_each_compatible_node(np, NULL, "ibm,plb-pcix") in ppc4xx_pci_find_bridges()
2076 for_each_compatible_node(np, NULL, "ibm,plb-pci") in ppc4xx_pci_find_bridges()