Lines Matching full:we
91 /* We need _PAGE_PRESENT and _PAGE_ACCESSED set */
93 /* We do the user/kernel test for the PID here along with the RW test
95 /* We pre-test some combination of permissions to avoid double
98 * We move the ESR:ST bit into the position of _PAGE_BAP_SW in the PTE
103 * writeable, we will take a new fault later, but that should be
106 * We also move ESR_ST in _PAGE_DIRTY position
109 * MAS1 is preset for all we need except for TID that needs to
137 * We are entered with:
176 /* Now we build the MAS:
219 /* We need to check if it was an instruction miss */
239 /* We do the user/kernel test for the PID here along with the RW test
253 * No HES or NV hint on TLB1, so we need to do software round-robin
254 * No tlbsrx. so we need a spinlock, and we have to deal
281 * We are entered with:
296 * Search if we already have an indirect entry for that virtual
297 * address, and if we do, bail out.
324 * Erratum A-008139 says that we can't use tlbwe to change
379 /* Now, we need to walk the page tables. First check if we are in
407 /* Now we build the MAS for a 2M indirect page:
456 * Now we build the MAS for a huge page.
499 /* We need to check if it was an instruction miss */
511 * misses. We are entered with:
523 * That means we can always get the original fault DEAR at
528 * 0 so we don't care too much about clobbers
530 * XXX That code was written back when we couldn't clobber r14. We can now,
531 * so we could probably optimize things a bit
534 /* Are we hitting a kernel page table ? */
539 * and we happen to have the swapper_pg_dir at offset 8 from the user
544 /* If kernel, we need to clear MAS1 TID */
561 /* Now, we need to walk the page tables. First check if we are in
594 /* Ok, we're all right, we can now create a kernel translation for
597 /* Now we build the MAS:
606 * So we only do MAS 2 and 3 for now...
622 /* If we fault here, things are a little bit tricky. We need to call
623 * either data or instruction store fault, and we need to retrieve
626 * The thing is, we know that in normal circumstances, this is
628 * level TLB miss for HW load, so we should be able to peek at the
631 * However, we do need to double check that, because we may just hit
633 * areas. If that is the case, we do a data fault. (We can't get here
636 * Note also that when going to a fault, we must unwind the previous
637 * level as well. Since we are doing that, we don't need to clear or
644 /* We dig the original DEAR and ESR from slot 0 */
648 /* We check for the "special" ESR value for instruction faults */
660 * not have been clobbered, let's just fault with what we have
667 * mapping misses. We are entered with:
678 * In addition we know that we will not re-enter, so in theory, we could
679 * use a simpler epilog not restoring SRR0/1 etc.. but we'll do that later.
681 * We also need to be careful about MAS registers here & TLB reservation,
682 * as we know we'll have clobbered them if we interrupt the main TLB miss
683 * handlers in which case we probably want to do a full restart at level
686 * Note: If we care about performance of that core, we can easily shuffle
690 /* For now, we assume the linear mapping is contiguous and stops at
691 * linear_map_top. We also assume the size is a multiple of 1G, thus
692 * we only use 1G pages for now. That might have to be changed in a
711 /* Now we build the remaining MAS. MAS0 and 2 should be fine
713 * mapping is linear, so we just take the address, clear the
728 /* We use the "error" epilog for success as we do want to
730 * We do that because we can't resume a fault within a TLB
737 /* We keep the DEAR and ESR around, this shouldn't have happened */