Lines Matching full:wp
109 u32 wp[2]; member
200 vc.wp[0] = current->thread.evr[fc]; in do_spe_mathemu()
201 vc.wp[1] = regs->gpr[fc]; in do_spe_mathemu()
202 va.wp[0] = current->thread.evr[fa]; in do_spe_mathemu()
203 va.wp[1] = regs->gpr[fa]; in do_spe_mathemu()
204 vb.wp[0] = current->thread.evr[fb]; in do_spe_mathemu()
205 vb.wp[1] = regs->gpr[fb]; in do_spe_mathemu()
210 pr_debug("vc: %08x %08x\n", vc.wp[0], vc.wp[1]); in do_spe_mathemu()
211 pr_debug("va: %08x %08x\n", va.wp[0], va.wp[1]); in do_spe_mathemu()
212 pr_debug("vb: %08x %08x\n", vb.wp[0], vb.wp[1]); in do_spe_mathemu()
221 FP_UNPACK_SP(SA, va.wp + 1); in do_spe_mathemu()
224 FP_UNPACK_SP(SB, vb.wp + 1); in do_spe_mathemu()
227 FP_UNPACK_SP(SA, va.wp + 1); in do_spe_mathemu()
236 vc.wp[1] = va.wp[1] & ~SIGN_BIT_S; in do_spe_mathemu()
240 vc.wp[1] = va.wp[1] | SIGN_BIT_S; in do_spe_mathemu()
244 vc.wp[1] = va.wp[1] ^ SIGN_BIT_S; in do_spe_mathemu()
278 vc.wp[1] = 0; in do_spe_mathemu()
282 FP_TO_INT_ROUND_S(vc.wp[1], SB, 32, in do_spe_mathemu()
302 vc.wp[1] = 0; in do_spe_mathemu()
305 FP_TO_INT_ROUND_S(vc.wp[1], SB, 32, in do_spe_mathemu()
313 vc.wp[1] = 0; in do_spe_mathemu()
316 FP_TO_INT_S(vc.wp[1], SB, 32, in do_spe_mathemu()
329 FP_PACK_SP(vc.wp + 1, SR); in do_spe_mathemu()
409 vc.wp[1] = 0; in do_spe_mathemu()
413 FP_TO_INT_ROUND_D(vc.wp[1], DB, 32, in do_spe_mathemu()
421 FP_UNPACK_SP(SB, vb.wp + 1); in do_spe_mathemu()
444 vc.wp[1] = 0; in do_spe_mathemu()
447 FP_TO_INT_ROUND_D(vc.wp[1], DB, 32, in do_spe_mathemu()
455 vc.wp[1] = 0; in do_spe_mathemu()
458 FP_TO_INT_D(vc.wp[1], DB, 32, in do_spe_mathemu()
496 FP_UNPACK_SP(SA0, va.wp); in do_spe_mathemu()
497 FP_UNPACK_SP(SA1, va.wp + 1); in do_spe_mathemu()
500 FP_UNPACK_SP(SB0, vb.wp); in do_spe_mathemu()
501 FP_UNPACK_SP(SB1, vb.wp + 1); in do_spe_mathemu()
504 FP_UNPACK_SP(SA0, va.wp); in do_spe_mathemu()
505 FP_UNPACK_SP(SA1, va.wp + 1); in do_spe_mathemu()
520 vc.wp[0] = va.wp[0] & ~SIGN_BIT_S; in do_spe_mathemu()
521 vc.wp[1] = va.wp[1] & ~SIGN_BIT_S; in do_spe_mathemu()
525 vc.wp[0] = va.wp[0] | SIGN_BIT_S; in do_spe_mathemu()
526 vc.wp[1] = va.wp[1] | SIGN_BIT_S; in do_spe_mathemu()
530 vc.wp[0] = va.wp[0] ^ SIGN_BIT_S; in do_spe_mathemu()
531 vc.wp[1] = va.wp[1] ^ SIGN_BIT_S; in do_spe_mathemu()
569 vc.wp[0] = 0; in do_spe_mathemu()
573 FP_TO_INT_ROUND_S(vc.wp[0], SB0, 32, in do_spe_mathemu()
577 vc.wp[1] = 0; in do_spe_mathemu()
581 FP_TO_INT_ROUND_S(vc.wp[1], SB1, 32, in do_spe_mathemu()
589 vc.wp[0] = 0; in do_spe_mathemu()
592 FP_TO_INT_ROUND_S(vc.wp[0], SB0, 32, in do_spe_mathemu()
596 vc.wp[1] = 0; in do_spe_mathemu()
599 FP_TO_INT_ROUND_S(vc.wp[1], SB1, 32, in do_spe_mathemu()
607 vc.wp[0] = 0; in do_spe_mathemu()
610 FP_TO_INT_S(vc.wp[0], SB0, 32, in do_spe_mathemu()
614 vc.wp[1] = 0; in do_spe_mathemu()
617 FP_TO_INT_S(vc.wp[1], SB1, 32, in do_spe_mathemu()
633 FP_PACK_SP(vc.wp, SR0); in do_spe_mathemu()
634 FP_PACK_SP(vc.wp + 1, SR1); in do_spe_mathemu()
685 current->thread.evr[fc] = vc.wp[0]; in do_spe_mathemu()
686 regs->gpr[fc] = vc.wp[1]; in do_spe_mathemu()
691 pr_debug("vc: %08x %08x\n", vc.wp[0], vc.wp[1]); in do_spe_mathemu()
692 pr_debug("va: %08x %08x\n", va.wp[0], va.wp[1]); in do_spe_mathemu()
693 pr_debug("vb: %08x %08x\n", vb.wp[0], vb.wp[1]); in do_spe_mathemu()
757 fgpr.wp[0] = current->thread.evr[fc]; in speround_handler()
758 fgpr.wp[1] = regs->gpr[fc]; in speround_handler()
791 if (fgpr.wp[1] == 0) in speround_handler()
799 if (fgpr.wp[1] == 0) in speround_handler()
801 if (fgpr.wp[0] == 0) in speround_handler()
810 if (fgpr.wp[1] == 0) in speround_handler()
819 pr_debug("round fgpr: %08x %08x\n", fgpr.wp[0], fgpr.wp[1]); in speround_handler()
828 if (!s_lo) fgpr.wp[1]++; /* Z > 0, choose Z1 */ in speround_handler()
832 fgpr.wp[1]++; /* Z < 0, choose Z2 */ in speround_handler()
834 fgpr.wp[1]--; /* Z < 0, choose Z2 */ in speround_handler()
845 fgpr.wp[1]++; /* Z > 0, choose Z1 */ in speround_handler()
852 fgpr.wp[1]--; /* Z < 0, choose Z2 */ in speround_handler()
860 fgpr.wp[1]++; /* Z_low > 0, choose Z1 */ in speround_handler()
862 fgpr.wp[0]++; /* Z_high word > 0, choose Z1 */ in speround_handler()
866 fgpr.wp[1]++; /* Z_low < 0, choose Z2 */ in speround_handler()
868 fgpr.wp[1]--; /* Z_low < 0, choose Z2 */ in speround_handler()
872 fgpr.wp[0]++; /* Z_high < 0, choose Z2 */ in speround_handler()
874 fgpr.wp[0]--; /* Z_high < 0, choose Z2 */ in speround_handler()
883 current->thread.evr[fc] = fgpr.wp[0]; in speround_handler()
884 regs->gpr[fc] = fgpr.wp[1]; in speround_handler()
886 pr_debug(" to fgpr: %08x %08x\n", fgpr.wp[0], fgpr.wp[1]); in speround_handler()