62 #define IS_LE	1  macro
65 #define IS_LE	0  macro
749 		err = read_mem(&regs->gpr[reg + IS_LE], ea, 8, regs);  in emulate_lq()
775 	err = write_mem(vals[IS_LE], ea, 8, regs);  in emulate_stq()
803 		if (IS_LE && (op->vsx_flags & VSX_LDLEFT))  in emulate_vsx_load()
811 		i = IS_LE ? 8 : 8 - read_size;  in emulate_vsx_load()
818 				reg->d[IS_LE] = (signed int) reg->d[IS_LE];  in emulate_vsx_load()
821 				conv_sp_to_dp(&reg->fp[1 + IS_LE],  in emulate_vsx_load()
822 					      &reg->dp[IS_LE]);  in emulate_vsx_load()
830 				reg->d[IS_BE] = reg->d[IS_LE];  in emulate_vsx_load()
837 			i = IS_LE ? 3 - j : j;  in emulate_vsx_load()
841 			u32 val = reg->w[IS_LE ? 3 : 0];  in emulate_vsx_load()
843 				i = IS_LE ? 3 - j : j;  in emulate_vsx_load()
852 			i = IS_LE ? 7 - j : j;  in emulate_vsx_load()
860 			i = IS_LE ? 15 - j : j;  in emulate_vsx_load()
902 		if (IS_LE && (op->vsx_flags & VSX_LDLEFT))  in emulate_vsx_store()
915 		i = IS_LE ? 8 : 8 - write_size;  in emulate_vsx_store()
919 			conv_dp_to_sp(&reg->dp[IS_LE], &buf.fp[1 + IS_LE]);  in emulate_vsx_store()
936 			i = IS_LE ? 3 - j : j;  in emulate_vsx_store()
944 			i = IS_LE ? 7 - j : j;  in emulate_vsx_store()
952 			i = IS_LE ? 15 - j : j;  in emulate_vsx_store()
981 				j = IS_LE ? nr_vsx_regs - i - 1 : i;  in do_vsx_load()
986 				j = IS_LE ? nr_vsx_regs - i - 1 : i;  in do_vsx_load()
994 				j = IS_LE ? nr_vsx_regs - i - 1 : i;  in do_vsx_load()
999 				j = IS_LE ? nr_vsx_regs - i - 1 : i;  in do_vsx_load()
1027 				j = IS_LE ? nr_vsx_regs - i - 1 : i;  in do_vsx_store()
1032 				j = IS_LE ? nr_vsx_regs - i - 1 : i;  in do_vsx_store()
1040 				j = IS_LE ? nr_vsx_regs - i - 1 : i;  in do_vsx_store()
1045 				j = IS_LE ? nr_vsx_regs - i - 1 : i;  in do_vsx_store()