46 	struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu;  in kvmppc_xive_native_cleanup_queue()  local
47 	struct xive_q *q = &xc->queues[prio];  in kvmppc_xive_native_cleanup_queue()
49 	xive_native_disable_queue(xc->vp_id, q, prio);  in kvmppc_xive_native_cleanup_queue()
76 	struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu;  in kvmppc_xive_native_cleanup_vcpu()  local
82 	if (!xc)  in kvmppc_xive_native_cleanup_vcpu()
85 	pr_devel("native_cleanup_vcpu(cpu=%d)\n", xc->server_num);  in kvmppc_xive_native_cleanup_vcpu()
88 	xc->valid = false;  in kvmppc_xive_native_cleanup_vcpu()
92 	for (i = 0; i < KVMPPC_XIVE_Q_COUNT; i++) {  in kvmppc_xive_native_cleanup_vcpu()
94 		if (xc->esc_virq[i]) {  in kvmppc_xive_native_cleanup_vcpu()
95 			if (kvmppc_xive_has_single_escalation(xc->xive))  in kvmppc_xive_native_cleanup_vcpu()
96 				xive_cleanup_single_escalation(vcpu, xc->esc_virq[i]);  in kvmppc_xive_native_cleanup_vcpu()
97 			free_irq(xc->esc_virq[i], vcpu);  in kvmppc_xive_native_cleanup_vcpu()
98 			irq_dispose_mapping(xc->esc_virq[i]);  in kvmppc_xive_native_cleanup_vcpu()
99 			kfree(xc->esc_virq_names[i]);  in kvmppc_xive_native_cleanup_vcpu()
100 			xc->esc_virq[i] = 0;  in kvmppc_xive_native_cleanup_vcpu()
105 	xive_native_disable_vp(xc->vp_id);  in kvmppc_xive_native_cleanup_vcpu()
108 	vcpu->arch.xive_cam_word = 0;  in kvmppc_xive_native_cleanup_vcpu()
111 	for (i = 0; i < KVMPPC_XIVE_Q_COUNT; i++) {  in kvmppc_xive_native_cleanup_vcpu()
116 	kfree(xc);  in kvmppc_xive_native_cleanup_vcpu()
127 	struct kvmppc_xive_vcpu *xc = NULL;  in kvmppc_xive_native_connect_vcpu()  local
148 	xc = kzalloc(sizeof(*xc), GFP_KERNEL);  in kvmppc_xive_native_connect_vcpu()
149 	if (!xc) {  in kvmppc_xive_native_connect_vcpu()
154 	vcpu->arch.xive_vcpu = xc;  in kvmppc_xive_native_connect_vcpu()
155 	xc->xive = xive;  in kvmppc_xive_native_connect_vcpu()
156 	xc->vcpu = vcpu;  in kvmppc_xive_native_connect_vcpu()
157 	xc->server_num = server_num;  in kvmppc_xive_native_connect_vcpu()
159 	xc->vp_id = vp_id;  in kvmppc_xive_native_connect_vcpu()
160 	xc->valid = true;  in kvmppc_xive_native_connect_vcpu()
163 	rc = xive_native_get_vp_info(xc->vp_id, &xc->vp_cam, &xc->vp_chip_id);  in kvmppc_xive_native_connect_vcpu()
179 	rc = xive_native_enable_vp(xc->vp_id, kvmppc_xive_has_single_escalation(xive));  in kvmppc_xive_native_connect_vcpu()
186 	vcpu->arch.xive_saved_state.w01 = cpu_to_be64(0xff000000);  in kvmppc_xive_native_connect_vcpu()
187 	vcpu->arch.xive_cam_word = cpu_to_be32(xc->vp_cam | TM_QW1W2_VO);  in kvmppc_xive_native_connect_vcpu()
214 	pr_debug("clearing esb pages for girq 0x%lx\n", irq);  in kvmppc_xive_native_reset_mapped()
221 	return 0;  in kvmppc_xive_native_reset_mapped()
293 	case 0: /* HW - forbid access */  in xive_native_tima_fault()
336 	return 0;  in kvmppc_xive_native_mmap()
349 	pr_devel("%s irq=0x%lx\n", __func__, irq);  in kvmppc_xive_native_set_source()
378 		if (state->ipi_number == 0) {  in kvmppc_xive_native_set_source()
385 		pr_debug("%s allocated hw_irq=0x%x for irq=0x%lx\n", __func__,  in kvmppc_xive_native_set_source()
398 	state->act_server = 0;  in kvmppc_xive_native_set_source()
401 	xive_native_configure_irq(state->ipi_number, 0, MASKED, 0);  in kvmppc_xive_native_set_source()
408 	rc = 0;  in kvmppc_xive_native_set_source()
424 	int rc = 0;  in kvmppc_xive_native_update_source_config()
452 		state->act_server = 0;  in kvmppc_xive_native_update_source_config()
453 		state->eisn = 0;  in kvmppc_xive_native_update_source_config()
455 		rc = xive_native_configure_irq(hw_num, 0, MASKED, 0);  in kvmppc_xive_native_update_source_config()
488 	pr_devel("%s irq=0x%lx cfg=%016llx\n", __func__, irq, kvm_cfg);  in kvmppc_xive_native_set_source_config()
517 	int rc = 0;  in kvmppc_xive_native_sync_source()
519 	pr_devel("%s irq=0x%lx", __func__, irq);  in kvmppc_xive_native_sync_source()
534 		rc = 0;  in kvmppc_xive_native_sync_source()
548 	case 0: /* EQ reset */  in xive_native_validate_queue_size()
550 		return 0;  in xive_native_validate_queue_size()
564 	struct kvmppc_xive_vcpu *xc;  in kvmppc_xive_native_set_queue_config()  local
593 	xc = vcpu->arch.xive_vcpu;  in kvmppc_xive_native_set_queue_config()
600 	q = &xc->queues[priority];  in kvmppc_xive_native_set_queue_config()
608 		q->guest_qaddr  = 0;  in kvmppc_xive_native_set_queue_config()
609 		q->guest_qshift = 0;  in kvmppc_xive_native_set_queue_config()
611 		rc = kvmppc_xive_native_configure_queue(xc->vp_id, q, priority,  in kvmppc_xive_native_set_queue_config()
612 							NULL, 0, true);  in kvmppc_xive_native_set_queue_config()
615 			       priority, xc->server_num, rc);  in kvmppc_xive_native_set_queue_config()
619 		return 0;  in kvmppc_xive_native_set_queue_config()
678 	rc = kvmppc_xive_native_configure_queue(xc->vp_id, q, priority,  in kvmppc_xive_native_set_queue_config()
682 		       priority, xc->server_num, rc);  in kvmppc_xive_native_set_queue_config()
691 	if (kvm_eq.qtoggle != 1 || kvm_eq.qindex != 0) {  in kvmppc_xive_native_set_queue_config()
692 		rc = xive_native_set_queue_state(xc->vp_id, priority,  in kvmppc_xive_native_set_queue_config()
712 	struct kvmppc_xive_vcpu *xc;  in kvmppc_xive_native_get_queue_config()  local
738 	xc = vcpu->arch.xive_vcpu;  in kvmppc_xive_native_get_queue_config()
745 	q = &xc->queues[priority];  in kvmppc_xive_native_get_queue_config()
747 	memset(&kvm_eq, 0, sizeof(kvm_eq));  in kvmppc_xive_native_get_queue_config()
750 		return 0;  in kvmppc_xive_native_get_queue_config()
752 	rc = xive_native_get_queue_info(xc->vp_id, priority, &qaddr, &qshift,  in kvmppc_xive_native_get_queue_config()
757 	kvm_eq.flags = 0;  in kvmppc_xive_native_get_queue_config()
764 	rc = xive_native_get_queue_state(xc->vp_id, priority, &kvm_eq.qtoggle,  in kvmppc_xive_native_get_queue_config()
776 	return 0;  in kvmppc_xive_native_get_queue_config()
783 	for (i = 0; i < KVMPPC_XICS_IRQ_PER_ICS; i++) {  in kvmppc_xive_reset_sources()
792 		state->eisn = 0;  in kvmppc_xive_reset_sources()
793 		state->act_server = 0;  in kvmppc_xive_reset_sources()
796 		xive_native_configure_irq(state->ipi_number, 0, MASKED, 0);  in kvmppc_xive_reset_sources()
800 						  0, MASKED, 0);  in kvmppc_xive_reset_sources()
816 		struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu;  in kvmppc_xive_reset()  local
819 		if (!xc)  in kvmppc_xive_reset()
824 		for (prio = 0; prio < KVMPPC_XIVE_Q_COUNT; prio++) {  in kvmppc_xive_reset()
830 			if (xc->esc_virq[prio]) {  in kvmppc_xive_reset()
831 				free_irq(xc->esc_virq[prio], vcpu);  in kvmppc_xive_reset()
832 				irq_dispose_mapping(xc->esc_virq[prio]);  in kvmppc_xive_reset()
833 				kfree(xc->esc_virq_names[prio]);  in kvmppc_xive_reset()
834 				xc->esc_virq[prio] = 0;  in kvmppc_xive_reset()
841 	for (i = 0; i <= xive->max_sbid; i++) {  in kvmppc_xive_reset()
853 	return 0;  in kvmppc_xive_reset()
860 	for (j = 0; j < KVMPPC_XICS_IRQ_PER_ICS; j++) {  in kvmppc_xive_native_sync_sources()
893 	struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu;  in kvmppc_xive_native_vcpu_eq_sync()  local
897 	if (!xc)  in kvmppc_xive_native_vcpu_eq_sync()
900 	for (prio = 0; prio < KVMPPC_XIVE_Q_COUNT; prio++) {  in kvmppc_xive_native_vcpu_eq_sync()
901 		struct xive_q *q = &xc->queues[prio];  in kvmppc_xive_native_vcpu_eq_sync()
911 	return 0;  in kvmppc_xive_native_vcpu_eq_sync()
923 	for (i = 0; i <= xive->max_sbid; i++) {  in kvmppc_xive_native_eq_sync()
938 	return 0;  in kvmppc_xive_native_eq_sync()
995 			return 0;  in kvmppc_xive_native_has_attr()
1003 			return 0;  in kvmppc_xive_native_has_attr()
1006 		return 0;  in kvmppc_xive_native_has_attr()
1068 	for (i = 0; i <= xive->max_sbid; i++) {  in kvmppc_xive_native_release()
1127 	return 0;  in kvmppc_xive_native_create()
1134 #define TM_IPB_MASK  (((u64) 0xFF) << TM_IPB_SHIFT)
1138 	struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu;  in kvmppc_xive_native_get_vp()  local
1145 	if (!xc)  in kvmppc_xive_native_get_vp()
1149 	val->xive_timaval[0] = vcpu->arch.xive_saved_state.w01;  in kvmppc_xive_native_get_vp()
1152 	rc = xive_native_get_vp_state(xc->vp_id, &opal_state);  in kvmppc_xive_native_get_vp()
1160 	val->xive_timaval[0] |= cpu_to_be64(opal_state & TM_IPB_MASK);  in kvmppc_xive_native_get_vp()
1171 	return 0;  in kvmppc_xive_native_get_vp()
1176 	struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu;  in kvmppc_xive_native_set_vp()  local
1180 		 val->xive_timaval[0], val->xive_timaval[1]);  in kvmppc_xive_native_set_vp()
1185 	if (!xc || !xive)  in kvmppc_xive_native_set_vp()
1196 	vcpu->arch.xive_saved_state.w01 = val->xive_timaval[0];  in kvmppc_xive_native_set_vp()
1203 	return 0;  in kvmppc_xive_native_set_vp()
1219 		return 0;  in xive_native_debug_show()
1224 		struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu;  in xive_native_debug_show()  local
1226 		if (!xc)  in xive_native_debug_show()
1231 			   xc->server_num, xc->vp_id, xc->vp_chip_id,  in xive_native_debug_show()
1244 	for (i = 0; i <= xive->max_sbid; i++) {  in xive_native_debug_show()
1254 	return 0;  in xive_native_debug_show()