Lines Matching full:std
73 std r0, PPC_LR_STKOFF(r1)
76 std r10, HSTATE_HOST_MSR(r13)
270 std r5, 8(r1) // Save CR in caller's frame
271 std r0, 16(r1) // Save LR in caller's frame
277 std r3, 32(r1) // Save SRR1 wakeup value
331 std r0, 32(r1)
335 std r6, HSTATE_DSCR(r13)
363 std r0, HSTATE_KVM_VCPU(r13)
371 std r0, HSTATE_KVM_VCORE(r13)
518 std r0, PPC_LR_STKOFF(r1)
522 std r1, HSTATE_HOST_R1(r13)
581 std r8, VCORE_TB_OFFSET_APPL(r5)
637 std r5,HSTATE_PURR(r13)
638 std r6,HSTATE_SPURR(r13)
650 std r5, STACK_SLOT_CIABR(r1)
651 std r6, STACK_SLOT_DAWR0(r1)
652 std r7, STACK_SLOT_DAWRX0(r1)
653 std r8, STACK_SLOT_IAMR(r1)
655 std r5, STACK_SLOT_FSCR(r1)
659 std r5, STACK_SLOT_AMR(r1)
661 std r6, STACK_SLOT_UAMOR(r1)
1000 std r0, VCPU_GPR(R0)(r9)
1001 std r1, VCPU_GPR(R1)(r9)
1002 std r2, VCPU_GPR(R2)(r9)
1003 std r3, VCPU_GPR(R3)(r9)
1004 std r4, VCPU_GPR(R4)(r9)
1005 std r5, VCPU_GPR(R5)(r9)
1006 std r6, VCPU_GPR(R6)(r9)
1007 std r7, VCPU_GPR(R7)(r9)
1008 std r8, VCPU_GPR(R8)(r9)
1010 std r0, VCPU_GPR(R9)(r9)
1011 std r10, VCPU_GPR(R10)(r9)
1012 std r11, VCPU_GPR(R11)(r9)
1014 std r3, VCPU_GPR(R12)(r9)
1017 std r4, VCPU_CR(r9)
1020 std r3, VCPU_CFAR(r9)
1024 std r4, VCPU_PPR(r9)
1033 std r10, VCPU_SRR0(r9)
1034 std r11, VCPU_SRR1(r9)
1042 1: std r10, VCPU_PC(r9)
1043 std r11, VCPU_MSR(r9)
1047 std r3, VCPU_GPR(R13)(r9)
1048 std r4, VCPU_LR(r9)
1074 std r3,VCPU_LAST_INST(r9)
1078 11: std r3,VCPU_HEIR(r9)
1083 std r3, VCPU_CTR(r9)
1084 std r4, VCPU_XER(r9)
1089 std r3, VCPU_DAR(r9)
1095 std r3, VCPU_FAULT_DAR(r9)
1125 std r3, VCPU_HFSCR(r9)
1164 std r8,VCPU_SLB_E(r7)
1165 std r3,VCPU_SLB_V(r7)
1201 std r5,VCPU_DEC_EXPIRES(r9)
1229 std r5,VCPU_PURR(r9)
1230 std r6,VCPU_SPURR(r9)
1252 std r5, VCPU_IAMR(r9)
1254 std r7, VCPU_FSCR(r9)
1257 std r5, VCPU_IC(r9)
1258 std r7, VCPU_TAR(r9)
1260 std r8, VCPU_EBBHR(r9)
1265 std r5, VCPU_EBBRR(r9)
1266 std r6, VCPU_BESCR(r9)
1268 std r8, VCPU_WORT(r9)
1273 std r5, VCPU_TCSCR(r9)
1274 std r6, VCPU_ACOP(r9)
1275 std r7, VCPU_CSIGR(r9)
1276 std r8, VCPU_TACR(r9)
1301 std r5,VCPU_AMR(r9)
1302 std r6,VCPU_UAMOR(r9)
1311 std r8, VCPU_DSCR(r9)
1315 std r14, VCPU_GPR(R14)(r9)
1316 std r15, VCPU_GPR(R15)(r9)
1317 std r16, VCPU_GPR(R16)(r9)
1318 std r17, VCPU_GPR(R17)(r9)
1319 std r18, VCPU_GPR(R18)(r9)
1320 std r19, VCPU_GPR(R19)(r9)
1321 std r20, VCPU_GPR(R20)(r9)
1322 std r21, VCPU_GPR(R21)(r9)
1323 std r22, VCPU_GPR(R22)(r9)
1324 std r23, VCPU_GPR(R23)(r9)
1325 std r24, VCPU_GPR(R24)(r9)
1326 std r25, VCPU_GPR(R25)(r9)
1327 std r26, VCPU_GPR(R26)(r9)
1328 std r27, VCPU_GPR(R27)(r9)
1329 std r28, VCPU_GPR(R28)(r9)
1330 std r29, VCPU_GPR(R29)(r9)
1331 std r30, VCPU_GPR(R30)(r9)
1332 std r31, VCPU_GPR(R31)(r9)
1339 std r3, VCPU_SPRG0(r9)
1340 std r4, VCPU_SPRG1(r9)
1341 std r5, VCPU_SPRG2(r9)
1342 std r6, VCPU_SPRG3(r9)
1445 std r7, VCORE_DPDES(r5)
1446 std r8, VCORE_VTB(r5)
1457 std r0, VCORE_TB_OFFSET_APPL(r5)
1623 4: std r4, VCPU_FAULT_DAR(r9)
1679 std r8, VCPU_LAST_INST(r9)
1768 std r3,VCPU_GPR(R3)(r4)
2017 std r4,VCPU_DABR(r3)
2041 std r4, VCPU_DAWR0(r3)
2042 std r5, VCPU_DAWRX0(r3)
2059 std r11,VCPU_MSR(r3)
2069 std r0,VCPU_GPR(R3)(r3)
2104 std r14, VCPU_GPR(R14)(r3)
2105 std r15, VCPU_GPR(R15)(r3)
2106 std r16, VCPU_GPR(R16)(r3)
2107 std r17, VCPU_GPR(R17)(r3)
2108 std r18, VCPU_GPR(R18)(r3)
2109 std r19, VCPU_GPR(R19)(r3)
2110 std r20, VCPU_GPR(R20)(r3)
2111 std r21, VCPU_GPR(R21)(r3)
2112 std r22, VCPU_GPR(R22)(r3)
2113 std r23, VCPU_GPR(R23)(r3)
2114 std r24, VCPU_GPR(R24)(r3)
2115 std r25, VCPU_GPR(R25)(r3)
2116 std r26, VCPU_GPR(R26)(r3)
2117 std r27, VCPU_GPR(R27)(r3)
2118 std r28, VCPU_GPR(R28)(r3)
2119 std r29, VCPU_GPR(R29)(r3)
2120 std r30, VCPU_GPR(R30)(r3)
2121 std r31, VCPU_GPR(R31)(r3)
2158 std r3, VCPU_DEC_EXPIRES(r4)
2414 std r0, PPC_LR_STKOFF(r1)
2531 std r0, PPC_LR_STKOFF(r1)
2563 std r1, HSTATE_HOST_R1(r13)
2607 std r5, VCPU_TFHAR(r9)
2608 std r6, VCPU_TFIAR(r9)
2634 std r0, PPC_LR_STKOFF(r1)
2694 std r1, PACAR1(r13)
2697 std r9, 0(r1)
2698 std r0, GPR0(r1)
2699 std r9, GPR1(r1)
2700 std r2, GPR2(r1)
2704 std r0, _CCR(r1)
2705 std r12, _TRAP(r1)
2717 2: std r3, _NIP(r1)
2718 std r4, _MSR(r1)
2719 std r5, _DAR(r1)
2720 std r6, _DSISR(r1)
2725 std r0, GPR13(r1)
2728 std r5, ORIG_GPR3(r1)
2733 std r3, _LINK(r1)
2734 std r4, _CTR(r1)
2735 std r5, _XER(r1)
2736 std r6, SOFTE(r1)
2739 std r3, STACK_INT_FRAME_MARKER(r1)
2917 std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */
2922 std r4, VCPU_MMCR(r9)
2923 std r5, VCPU_MMCR + 8(r9)
2924 std r6, VCPU_MMCRA(r9)
2926 std r10, VCPU_MMCR + 16(r9)
2928 std r7, VCPU_SIAR(r9)
2929 std r8, VCPU_SDAR(r9)
2944 std r5, VCPU_SIER(r9)
2950 std r8, VCPU_MMCRS(r9)
2985 std r3, VCPU_CUR_ACTIVITY(r4)
2986 std r5, VCPU_ACTIVITY_START(r4)
2998 std r3, VCPU_CUR_ACTIVITY(r4)
3001 std r7, VCPU_ACTIVITY_START(r4)
3008 std r8, TAS_SEQCOUNT(r5)
3012 std r7, TAS_TOTAL(r5)
3018 3: std r3, TAS_MIN(r5)
3021 std r3, TAS_MAX(r5)
3024 std r8, TAS_SEQCOUNT(r5)