Lines Matching +full:4 +full:- +full:byte
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
23 .Lsig_start = . - 4
39 /* Register r1 can be found at offset 4 of a pt_regs structure.
42 .byte 0x0f; /* DW_CFA_def_cfa_expression */ \
43 .uleb128 9f - 1f; /* length */ \
45 .byte 0x71; .sleb128 PTREGS; /* DW_OP_breg1 */ \
46 .byte 0x06; /* DW_OP_deref */ \
47 .byte 0x23; .uleb128 RSIZE; /* DW_OP_plus_uconst */ \
48 .byte 0x06; /* DW_OP_deref */ \
54 .byte 0x10; /* DW_CFA_expression */ \
56 .uleb128 9f - 1f; /* length */ \
58 .byte 0x71; .sleb128 PTREGS; /* DW_OP_breg1 */ \
59 .byte 0x06; /* DW_OP_deref */ \
61 .byte 0x23; .uleb128 ofs; /* DW_OP_plus_uconst */ \
70 .byte 0x10; /* DW_CFA_expression */ \
72 .uleb128 9f - 1f; /* length */ \
74 .byte 0x30 + regno; /* DW_OP_lit0 */ \
76 .byte 0x40; /* DW_OP_lit16 */ \
77 .byte 0x1e; /* DW_OP_mul */ \
79 .byte 0x71; .sleb128 PTREGS; /* DW_OP_breg1 */ \
80 .byte 0x06; /* DW_OP_deref */ \
81 .byte 0x12; /* DW_OP_dup */ \
82 .byte 0x23; /* DW_OP_plus_uconst */ \
84 .byte 0x06; /* DW_OP_deref */ \
85 .byte 0x0c; .long 1 << 25; /* DW_OP_const4u */ \
86 .byte 0x1a; /* DW_OP_and */ \
87 .byte 0x12; /* DW_OP_dup, ret 0 if bra taken */ \
88 .byte 0x30; /* DW_OP_lit0 */ \
89 .byte 0x29; /* DW_OP_eq */ \
90 .byte 0x28; .short 0x7fff; /* DW_OP_bra to end */ \
91 .byte 0x13; /* DW_OP_drop, pop the 0 */ \
92 .byte 0x23; .uleb128 VREGS; /* DW_OP_plus_uconst */ \
93 .byte 0x22; /* DW_OP_plus */ \
94 .byte 0x2f; .short 0x7fff; /* DW_OP_skip to end */ \
100 .byte 0x10; /* DW_CFA_expression */ \
102 .uleb128 9f - 1f; /* length */ \
104 .byte 0x30 + regno; /* DW_OP_lit n */ \
105 .byte 0x2f; .short 2b - 9f; /* DW_OP_skip */ \
111 .byte 0x10; /* DW_CFA_expression */ \
113 .uleb128 9f - 1f; /* length */ \
115 .byte 0x0a; .short ofs; /* DW_OP_const2u */ \
116 .byte 0x2f; .short 3b - 9f; /* DW_OP_skip */ \
121 .byte 0x10; /* DW_CFA_expression */ \
123 .uleb128 9f - 1f; /* length */ \
125 .byte 0x71; .sleb128 PTREGS; /* DW_OP_breg1 */ \
126 .byte 0x06; /* DW_OP_deref */ \
127 .byte 0x23; .uleb128 VREGS; /* DW_OP_plus_uconst */ \
128 .byte 0x23; .uleb128 ofs; /* DW_OP_plus_uconst */ \
135 #define RSIZE 4
146 rsave ( 4, 4*RSIZE); \
184 rsave (36, 48*RSIZE + 4*8); \
220 vsave_msr1 ( 4); \
255 .long .Lcie_end - .Lcie_start
258 .byte 1 /* Version number */
259 .string "zRS" /* NUL-terminated augmentation string */
260 .uleb128 4 /* Code alignment factor */
261 .sleb128 -4 /* Data alignment factor */
262 .byte 67 /* Return address register column, ap */
264 .byte 0x1b /* DW_EH_PE_pcrel | DW_EH_PE_sdata4. */
265 .byte 0x0c,1,0 /* DW_CFA_def_cfa: r1 ofs 0 */
266 .balign 4
269 .long .Lfde0_end - .Lfde0_start
271 .long .Lfde0_start - .Lcie /* CIE pointer. */
272 .long .Lsig_start - . /* PC start, length */
273 .long .Lsig_end - .Lsig_start
278 .balign 4
285 .long .Lfde1_end - .Lfde1_start
287 .long .Lfde1_start - .Lcie /* CIE pointer. */
288 .long .Lsigrt_start - . /* PC start, length */
289 .long .Lsigrt_end - .Lsigrt_start
294 .balign 4