powerpc/kernel/l2cr_6xx.S

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 	Copyright © 1997-1998 by PowerLogix R & D, Inc.
9 	- First public release, contributed by PowerLogix.
12 	- Terry: Made sure code disabled interrupts before running. (Previously
14 	- Terry: Updated for tentative G4 support.  4MB of memory is now flushed
16 	- Terry: Updated for workaround to HID0[DPM] processor bug
20 	- Terry: Added isync to correct for an errata.
23 	- DanM: Finally added the 7450 patch I've had for the past
24 		several months.  The L2CR is similar, but I'm going
25 		to assume the user of this functions knows what they
29 	Please e-mail updates to this file to me, thanks!
36 #include <asm/feature-fixups.h>
40 	When setting the L2CR register, you must do a few special
41 	things.  If you are enabling the cache, you must perform a
42 	global invalidate.  If you are disabling the cache, you must
43 	flush the cache contents first.  This routine takes care of
44 	doing these things.  When first enabling the cache, make sure
45 	you pass in the L2CR you want, as well as passing in the
47 	performed if the L2I bit is set in applyThis.  When enabling
48 	the cache, you should also set the L2E bit in applyThis.  If
49 	you want to modify the L2CR contents after the cache has been
50 	enabled, the recommended procedure is to first call
51 	__setL2CR(0) to disable the cache and then call it again with
52 	the new values for L2CR.  Examples:
54 	_setL2CR(0)		- disables the cache
55 	_setL2CR(0xB3A04000)	- enables my G3 upgrade card:
56 				- L2E set to turn on the cache
57 				- L2SIZ set to 1MB
58 				- L2CLK set to 1:1
59 				- L2RAM set to pipelined synchronous late-write
60 				- L2I set to perform a global invalidation
61 				- L2OH set to 0.5 nS
62 				- L2DF set because this upgrade card
66 	the correct setting for your card and then place them in the
69 	causes cache pushes from the L1 cache to go to the L2 cache
73 	Starting with the 7450, the bits in this register have moved
74 	or behave differently.  The Enable, Parity Enable, Size,
75 	and L2 Invalidate are the only bits that have not moved.
76 	The size is read-only for these processors with internal L2
77 	cache, and the invalidate is a control as well as status.
78 		-- Dan
82  * Summary: this procedure ignores the L2I bit in the value passed in,
83  * flushes the cache if it was already enabled, always invalidates the
84  * cache, then enables the cache if the L2E bit is set in the value
86  *   -- paulus.
91 	li	r3,-1
111 	/* Before we perform the global invalidation, we must disable dynamic
113 	 * DPM can possibly interfere with the state machine in the processor
114 	 * that invalidates the L2 cache tags.
122 	/* Get the current enable bit of the L2CR into r4 */
126 	rlwinm	r5,r3,0,0,0		/* r5 contains the new enable bit */
127 	rlwinm	r3,r3,0,11,9		/* Turn off the invalidate bit */
128 	rlwinm	r3,r3,0,1,31		/* Turn off the enable bit */
134 	/* Flush the cache. First, read the first 4MB of memory (physical) to
135 	 * put new data in the cache.  (Actually we only need
136 	 * the size of the L2 cache plus the size of the L1 cache, but 4MB will
140 	 /**** Might be a good idea to set L2DO here - to prevent instructions
141 	       from getting into the cache.  But since we invalidate
142 	       the next time we enable the cache it doesn't really matter.
144 	       The bit moved on the 7450.....
148 	/* Disable L2 prefetch on some 745x and try to ensure
152 	 * doesn't even bother doing the dcbf's here...
174 	addi	r4,r4,32		/* Go to start of next cache line */
178 	/* Now, flush the first 4MB of memory */
185 	addi	r4,r4,32		/* Go to start of next cache line */
189 	/* Set up the L2CR configuration bits (and switch L2 off) */
190 	/* CPU errata: Make sure the mtspr below is already in the
215 	/* On the 7450, we wait for the L2I bit to clear......
223 	/* Wait for the invalidation to complete */
228 11:	rlwinm	r3,r3,0,11,9		/* Turn off the L2I bit */
233 	/* See if we need to enable the cache */
237 	/* Enable the cache */
242 	/* Enable L2 HW prefetch on 744x/745x */
266 	/* Return the L2CR contents */
275  * Here is a similar routine for dealing with the L3 cache
276  * on the 745x family of chips
282 	li	r3,-1
298 	/* Get the current enable bit of the L3CR into r4 */
302 	rlwinm	r5,r3,0,0,0		/* r5 contains the new enable bit */
303 	rlwinm	r3,r3,0,22,20		/* Turn off the invalidate bit */
304 	rlwinm	r3,r3,0,2,31		/* Turn off the enable & PE bits */
305 	rlwinm	r3,r3,0,5,3		/* Turn off the clken bit */
310 	/* Flush the cache.
321 	addi	r4,r4,32		/* Go to start of next cache line */
325 	/* Set up the L3CR configuration bits (and switch L3 off) */
349 	/* We wait for the L3I bit to clear...... */
355 	rlwinm	r3,r3,0,5,3		/* Turn off the clken bit */
364 	/* See if we need to enable the cache */
368 	/* Enable the cache */
385 	/* Return the L3CR contents */
392 /* --- End of PowerLogix code ---
396 /* flush_disable_L1()	- Flush and disable L1 cache
416 	addi	r3,r3,0x0020	/* Go to start of next cache line */
427 	addi	r3,r3,0x0020	/* Go to start of next cache line */
431 	/* We can now disable the L1 cache (HID0:DCE, HID0:ICE) */
439 /* inval_enable_L1	- Invalidate and enable L1 cache
446 	/* Enable and then Flash inval the instruction & data cache */