powerpc/kernel/head_85xx.S

71 	li	r25,0			/* phys kernel start (low) */
72 	li	r24,0			/* CPU number */
73 	li	r23,0			/* phys kernel start (high) */
84 0:	mflr	r8
85 	addis	r3,r8,(is_second_reloc - 0b)@ha
86 	lwz	r19,(is_second_reloc - 0b)@l(r3)
103 	addis	r4,r8,(kernstart_addr - 0b)@ha
104 	addi	r4,r4,(kernstart_addr - 0b)@l
107 	addis	r6,r8,(memstart_addr - 0b)@ha
108 	addi	r6,r6,(memstart_addr - 0b)@l
124 	rlwinm	r6,r25,0,0x3ffffff		/* r6 = PHYS_START % 64M */
125 	rlwinm	r5,r4,0,0x3ffffff		/* r5 = KERNELBASE % 64M */
141  * boot loader and load a single entry in TLB1[0] to map the
154  * Later in mapin_ram we will correctly map lowmem, and resize TLB1[0]
160 	lwz     r20,0(r20)
168 	SET_IVOR(0,  CriticalInput);
211 	lwz	r24, 0(r24)
232 	li	r0,0
260 	stw	r23,0(r3)
263 	stw	r25,0(r3)
282 	stw	r5, 0(r4)	/* Save abatron_pteptrs at a fixed location */
283 	stw	r6, 0(r5)
314 	rlwinm.	r10, r11, 32 - _PAGE_PSIZE_SHIFT, 0x1e; /* get tsize*/	\
316 	rlwinm.	r12, r11, 0, 0, 20;	/* Extract pt base address */	\
319 	li	r10, 0;			/* clear r10 */			\
327 	rlwinm.	r12, r11, 0, 0, 20;	/* Extract pt base address */	\
335 	lwz	r11, 0(r11);		/* Get L1 entry */			\
336 	rlwinm.	r12, r11, 0, 0, 19;	/* Extract L2 (pte) base address */	\
339 	lwz	r11, 0(r12);		/* Get Linux PTE */
361 	CRITICAL_EXCEPTION(0x0100, CRITICAL, CriticalInput, unknown_exception)
364 	MCHECK_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
368 	NORMAL_EXCEPTION_PROLOG(0x300, DATA_STORAGE)
387 	EXCEPTION(0x0500, EXTERNAL, ExternalInput, do_IRQ)
399 	EXCEPTION(0x0800, FP_UNAVAIL, FloatingPointUnavailable, emulation_assist_interrupt)
404 	SYSCALL_ENTRY   0xc00 BOOKE_INTERRUPT_SYSCALL SPRN_SRR1
407 	EXCEPTION(0x2900, AP_UNAVAIL, AuxillaryProcessorUnavailable, unknown_exception)
414 	EXCEPTION(0x3100, FIT, FixedIntervalTimer, unknown_exception)
418 	CRITICAL_EXCEPTION(0x3200, WATCHDOG, WatchdogTimer, WatchdogException)
420 	CRITICAL_EXCEPTION(0x3200, WATCHDOG, WatchdogTimer, unknown_exception)
427 	stw	r11, THREAD_NORMSAVE(0)(r10)
456 	mfspr	r12,SPRN_MAS1		/* Set TID to 0 */
457 	rlwinm	r12,r12,0,16,1
469 	rlwinm.	r12,r12,0,0x3fff0000
489 	lwz	r13,0(r12)		/* Get upper pte bits */
506 	lwz	r11, THREAD_NORMSAVE(0)(r10)
519 	stw	r11, THREAD_NORMSAVE(0)(r10)
549 	mfspr	r12,SPRN_MAS1		/* Set TID to 0 */
550 	rlwinm	r12,r12,0,16,1
570 	rlwinm.	r12,r12,0,0x3fff0000
591 	lwz	r13,0(r12)		/* Get upper pte bits */
609 	lwz	r11, THREAD_NORMSAVE(0)(r10)
617 	NORMAL_EXCEPTION_PROLOG(0x2010, SPE_UNAVAIL)
625 	EXCEPTION(0x2020, SPE_UNAVAIL, SPEUnavailable, unknown_exception)
631 	NORMAL_EXCEPTION_PROLOG(0x2030, SPE_FP_DATA)
639 	NORMAL_EXCEPTION_PROLOG(0x2050, SPE_FP_ROUND)
645 	EXCEPTION(0x2040, SPE_FP_DATA, SPEFloatingPointData, unknown_exception)
646 	EXCEPTION(0x2050, SPE_FP_ROUND, SPEFloatingPointRound, unknown_exception)
651 	EXCEPTION(0x2060, PERFORMANCE_MONITOR, PerformanceMonitor, \
654 	EXCEPTION(0x2070, DOORBELL, Doorbell, doorbell_exception)
656 	CRITICAL_EXCEPTION(0x2080, DOORBELL_CRITICAL, \
665 	CRITICAL_EXCEPTION(0, GUEST_DBELL_CRIT, CriticalGuestDoorbell, \
669 	EXCEPTION(0, HV_SYSCALL, Hypercall, unknown_exception)
672 	EXCEPTION(0, HV_PRIV, Ehvpriv, unknown_exception)
694 	cmpwi	6, r10, 0			/* check for huge page */
709 	rlwinm  r15, r15, 2, 0, 29
712 	li	r16, 0
717 	lwz     r15, 0(r17)			/* r15 = next_tlbcam_idx */
725 	andi.	r16, r16, 0xfff
733 	lwz	r15, 0(r14)
734 100:	stw	r15, 0(r17)
760 1:	rlwimi	r12, r13, 20, 0, 11	/* grab RPN[32:43] */
775 	rlwinm	r10, r10, 0, ~_PAGE_EXEC	/* Clear SX on user pages */
777 	rlwimi	r13, r12, 0, 20, 31	/* Get RPN from PTE, merge w/ perms */
792 	rlwinm	r13, r13, 0, 0, 19	/* bottom bits used for WIMGE/etc */
813 	lwz	r11, THREAD_NORMSAVE(0)(r10)
841 	REST_32EVRS(0,r10,r5,THREAD_EVR0)
863 	.align	4,0
875 	rlwinm	r9,r9,16,0x3fff0000	/* turn PID into MAS6[SPID] */
876 	rlwimi	r9,r8,28,0x00000001	/* turn MSR[DS] into MAS6[SAS] */
879 	tlbsx	0,r3			/* must succeed */
883 	rlwinm	r9,r8,25,0x1f		/* r9 = log2(page size) */
953 	cmpi	0,r5,0
954 	SAVE_32EVRS(0, r4, r3, THREAD_EVR0)
956 	evmwumiaa evr6, evr6, evr6	/* evr6 <- ACC = 0 * 0 + ACC */
974 	li	r13,0
991 	lwz	r3,0(r3)
993 	li	r26,0		/* r26 safe? */
1004 	lwz	r4,0(r4)
1006 	rlwinm	r5,r5,0,~0x3ffffff	/* aligned 64M */
1012 	li	r4,0
1013 2:	li	r5,0		/* no device tree */
1014 	li	r6,0		/* not boot cpu */
1020 	stw	r24,0(r3)
1022 	li	r3,0
1033 	li	r0,0
1034 	stw	r0,0(r1)
1067 	lis     r7,0x1000               /* Set MAS0(TLBSEL) = 1 */
1102 	rlwinm	r7, r7, 0, ~(MSR_IS | MSR_DS)
1119 	andi.	r3,r3,0xfff
1121 	rlwinm	r4,r4,16,0x3fff0000	/* turn PID into MAS6[SPID] */
1123 1:	lis	r4,0x1000		/* Set MAS0(TLBSEL) = 1 */
1134 0:	mflr	r4
1135 	tlbsx	0,r4
1142 	rlwinm	r4,r4,0,~MAS0_ESEL_MASK
1157  * Restore to the address space 0 and also invalidate the tlb entry created
1161  * r5 - device tree virtual address. If r4 is 0, r5 is ignored.
1168 0:	mflr	r9
1169 	addi	r9,r9,1f - 0b
1190 1:	lis	r9,0x1000		/* Set MAS0(TLBSEL) = 1 */
1195 	rlwinm	r9,r9,0,2,31		/* Clear MAS1 Valid and IPPROT */
1200 	cmpwi	r4,0
1201 	cmpwi	cr1,r6,0
1203 	bne	3f			/* offset != 0 && is_boot_cpu */