Lines Matching +full:0 +full:x8004
21 li r10,0
83 li r3,0
153 rlwinm r3,r3,0,20,31
154 cmpwi 0,r3,0x0207
160 rlwinm r3,r3,0,20,31
161 cmpwi 0,r3,0x0100
165 /* Errata #3: Set L1OPQ_SIZE to 0x10 */
166 rlwinm r11,r11,0,9,6
167 oris r11,r11,0x0100
169 oris r11,r11,0x0002
170 /* Errata #5: Set DRLT_SIZE to 0x01 */
171 rlwinm r11,r11,0,5,2
172 oris r11,r11,0x0800
198 li r3,0
281 li r3,0
315 REST_32FPRS(0,r9)
324 #define CS_HID0 0
338 .balign L1_CACHE_BYTES,0
341 /* Called in normal context to backup CPU 0 state. This
362 cmplwi cr0,r3,0x8000 /* 7450 */
363 cmplwi cr1,r3,0x000c /* 7400 */
364 cmplwi cr2,r3,0x800c /* 7410 */
365 cmplwi cr3,r3,0x8001 /* 7455 */
366 cmplwi cr4,r3,0x8002 /* 7457 */
367 cmplwi cr5,r3,0x8003 /* 7447A */
368 cmplwi cr6,r3,0x7000 /* 750FX */
369 cmplwi cr7,r3,0x8004 /* 7448 */
401 andi. r3,r3,0xff00
402 cmpwi cr0,r3,0x0200
433 cmplwi cr0,r3,0x8000 /* 7450 */
434 cmplwi cr1,r3,0x000c /* 7400 */
435 cmplwi cr2,r3,0x800c /* 7410 */
436 cmplwi cr3,r3,0x8001 /* 7455 */
437 cmplwi cr4,r3,0x8002 /* 7457 */
438 cmplwi cr5,r3,0x8003 /* 7447A */
439 cmplwi cr6,r3,0x7000 /* 750FX */
440 cmplwi cr7,r3,0x8004 /* 7448 */
463 li r4,0
490 * to PLL 0 on all
494 andi. r3,r3,0xff00
495 cmpwi cr0,r3,0x0200
498 rlwinm r4,r4,0,19,17
503 rlwinm r5,r4,0,16,14