Lines Matching +full:0 +full:x00400000

18 #define TSI108_REG_SIZE		(0x10000)
21 #define TSI108_HLP_SIZE		0x1000
22 #define TSI108_PCI_SIZE		0x1000
23 #define TSI108_CLK_SIZE		0x1000
24 #define TSI108_PB_SIZE		0x1000
25 #define TSI108_SD_SIZE		0x1000
26 #define TSI108_DMA_SIZE		0x1000
27 #define TSI108_ETH_SIZE		0x1000
28 #define TSI108_I2C_SIZE		0x400
29 #define TSI108_MPIC_SIZE	0x400
30 #define TSI108_UART0_SIZE	0x200
31 #define TSI108_GPIO_SIZE	0x200
32 #define TSI108_UART1_SIZE	0x200
35 #define TSI108_HLP_OFFSET	0x0000
36 #define TSI108_PCI_OFFSET	0x1000
37 #define TSI108_CLK_OFFSET	0x2000
38 #define TSI108_PB_OFFSET	0x3000
39 #define TSI108_SD_OFFSET	0x4000
40 #define TSI108_DMA_OFFSET	0x5000
41 #define TSI108_ETH_OFFSET	0x6000
42 #define TSI108_I2C_OFFSET	0x7000
43 #define TSI108_MPIC_OFFSET	0x7400
44 #define TSI108_UART0_OFFSET	0x7800
45 #define TSI108_GPIO_OFFSET	0x7A00
46 #define TSI108_UART1_OFFSET	0x7C00
49 #define TSI108_PCI_CSR		(0x004)
50 #define TSI108_PCI_IRP_CFG_CTL	(0x180)
51 #define TSI108_PCI_IRP_STAT	(0x184)
52 #define TSI108_PCI_IRP_ENABLE	(0x188)
53 #define TSI108_PCI_IRP_INTAD	(0x18C)
55 #define TSI108_PCI_IRP_STAT_P_INT	(0x00400000)
56 #define TSI108_PCI_IRP_ENABLE_P_INT	(0x00400000)
58 #define TSI108_CG_PWRUP_STATUS	(0x234)
60 #define TSI108_PB_ISR		(0x00C)
61 #define TSI108_PB_ERRCS		(0x404)
62 #define TSI108_PB_AERR		(0x408)
67 #define TSI108_PCI_CFG_SIZE		(0x01000000)
75 #define TSI108_PHY_MV88E	0	/* Marvel 88Exxxx PHY */