Lines Matching full:compare
64 #define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */
65 #define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */
66 #define SPRN_DVC1 0x13E /* Data Value Compare Register 1 */
67 #define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */
162 #define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */
188 #define SPRN_IAC1 0x138 /* Instruction Address Compare 1 */
189 #define SPRN_IAC2 0x139 /* Instruction Address Compare 2 */
190 #define SPRN_DAC1 0x13C /* Data Address Compare 1 */
191 #define SPRN_DAC2 0x13D /* Data Address Compare 2 */
279 #define DBSR_IAC1 0x00800000 /* Instr Address Compare 1 Event */
280 #define DBSR_IAC2 0x00400000 /* Instr Address Compare 2 Event */
281 #define DBSR_IAC3 0x00200000 /* Instr Address Compare 3 Event */
282 #define DBSR_IAC4 0x00100000 /* Instr Address Compare 4 Event */
283 #define DBSR_DAC1R 0x00080000 /* Data Addr Compare 1 Read Event */
284 #define DBSR_DAC1W 0x00040000 /* Data Addr Compare 1 Write Event */
285 #define DBSR_DAC2R 0x00020000 /* Data Addr Compare 2 Read Event */
286 #define DBSR_DAC2W 0x00010000 /* Data Addr Compare 2 Write Event */
290 #define DBSR_IAC12ATS 0x00000002 /* Instr Address Compare 1/2 Toggle */
291 #define DBSR_IAC34ATS 0x00000001 /* Instr Address Compare 3/4 Toggle */
328 #define DBCR0_IAC1 0x00800000 /* Instr Addr compare 1 enable */
329 #define DBCR0_IAC2 0x00400000 /* Instr Addr compare 2 enable */
330 #define DBCR0_IAC3 0x00200000 /* Instr Addr compare 3 enable */
331 #define DBCR0_IAC4 0x00100000 /* Instr Addr compare 4 enable */