Lines Matching refs:ASM_CONST
268 #define TEXASR_FC (ASM_CONST(0xFF) << TEXASR_FC_LG)
422 #define FSCR_INTR_CAUSE (ASM_CONST(0xFF) << 56) /* interrupt cause */
437 #define LPCR_VPM0 ASM_CONST(0x8000000000000000)
438 #define LPCR_VPM1 ASM_CONST(0x4000000000000000)
439 #define LPCR_ISL ASM_CONST(0x2000000000000000)
442 #define LPCR_DPFD (ASM_CONST(7) << LPCR_DPFD_SH)
444 #define LPCR_VRMASD (ASM_CONST(0x1f) << LPCR_VRMASD_SH)
445 #define LPCR_VRMA_L ASM_CONST(0x0008000000000000)
446 #define LPCR_VRMA_LP0 ASM_CONST(0x0001000000000000)
447 #define LPCR_VRMA_LP1 ASM_CONST(0x0000800000000000)
450 #define LPCR_HAIL ASM_CONST(0x0000000004000000) /* HV AIL (ISAv3.1) */
451 #define LPCR_ILE ASM_CONST(0x0000000002000000) /* !HV irqs set MSR:LE */
452 #define LPCR_AIL ASM_CONST(0x0000000001800000) /* Alternate interrupt location */
453 #define LPCR_AIL_0 ASM_CONST(0x0000000000000000) /* MMU off exception offset 0x0 */
454 #define LPCR_AIL_3 ASM_CONST(0x0000000001800000) /* MMU on exception offset 0xc00...4xxx */
455 #define LPCR_ONL ASM_CONST(0x0000000000040000) /* online - PURR/SPURR count */
456 #define LPCR_LD ASM_CONST(0x0000000000020000) /* large decremeter */
457 #define LPCR_PECE ASM_CONST(0x000000000001f000) /* powersave exit cause enable */
458 #define LPCR_PECEDP ASM_CONST(0x0000000000010000) /* directed priv dbells cause exit */
459 #define LPCR_PECEDH ASM_CONST(0x0000000000008000) /* directed hyp dbells cause exit */
460 #define LPCR_PECE0 ASM_CONST(0x0000000000004000) /* ext. exceptions can cause exit */
461 #define LPCR_PECE1 ASM_CONST(0x0000000000002000) /* decrementer can cause exit */
462 #define LPCR_PECE2 ASM_CONST(0x0000000000001000) /* machine check etc can cause exit */
463 #define LPCR_PECE_HVEE ASM_CONST(0x0000400000000000) /* P9 Wakeup on HV interrupts */
464 #define LPCR_MER ASM_CONST(0x0000000000000800) /* Mediated External Exception */
466 #define LPCR_GTSE ASM_CONST(0x0000000000000400) /* Guest Translation Shootdown Enable */
467 #define LPCR_TC ASM_CONST(0x0000000000000200) /* Translation control */
468 #define LPCR_HEIC ASM_CONST(0x0000000000000010) /* Hypervisor External Interrupt Control */
470 #define LPCR_LPES0 ASM_CONST(0x0000000000000008) /* LPAR Env selector 0 */
471 #define LPCR_LPES1 ASM_CONST(0x0000000000000004) /* LPAR Env selector 1 */
473 #define LPCR_RMI ASM_CONST(0x0000000000000002) /* real mode is cache inhibit */
474 #define LPCR_HVICE ASM_CONST(0x0000000000000002) /* P9: HV interrupt enable */
475 #define LPCR_HDICE ASM_CONST(0x0000000000000001) /* Hyp Decr enable (HV,PR,EE) */
476 #define LPCR_UPRT ASM_CONST(0x0000000000400000) /* Use Process Table (ISA 3) */
477 #define LPCR_HR ASM_CONST(0x0000000000100000)
865 #define MMCR0_PMXE ASM_CONST(0x04000000) /* perf mon exception enable */
866 #define MMCR0_FCECE ASM_CONST(0x02000000) /* freeze ctrs on enabled cond or event */
871 #define MMCR0_PMCCEXT ASM_CONST(0x00000200) /* PMCCEXT control */
874 #define MMCR0_PMCjCE ASM_CONST(0x00004000) /* PMCj count enable*/
876 #define MMCR0_PMAO_SYNC ASM_CONST(0x00000800) /* PMU intr is synchronous */
877 #define MMCR0_C56RUN ASM_CONST(0x00000100) /* PMC5/6 count when RUN=0 */
879 #define MMCR0_PMAO ASM_CONST(0x00000080)