Lines Matching +full:0 +full:x00008000
9 #define BOOK3E_PAGESZ_1K 0
44 #define MAS0_TLBSEL_MASK 0x30000000
49 #define MAS0_ESEL_MASK 0x0FFF0000
52 #define MAS0_NV(x) ((x) & 0x00000FFF)
53 #define MAS0_HES 0x00004000
54 #define MAS0_WQ_ALLWAYS 0x00000000
55 #define MAS0_WQ_COND 0x00001000
56 #define MAS0_WQ_CLR_RSRV 0x00002000
58 #define MAS1_VALID 0x80000000
59 #define MAS1_IPROT 0x40000000
60 #define MAS1_TID(x) (((x) << 16) & 0x3FFF0000)
61 #define MAS1_IND 0x00002000
62 #define MAS1_TS 0x00001000
63 #define MAS1_TSIZE_MASK 0x00000f80
68 #define MAS2_EPN (~0xFFFUL)
69 #define MAS2_X0 0x00000040
70 #define MAS2_X1 0x00000020
71 #define MAS2_W 0x00000010
72 #define MAS2_I 0x00000008
73 #define MAS2_M 0x00000004
74 #define MAS2_G 0x00000002
75 #define MAS2_E 0x00000001
76 #define MAS2_WIMGE_MASK 0x0000001f
77 #define MAS2_EPN_MASK(size) (~0 << (size + 10))
79 #define MAS3_RPN 0xFFFFF000
80 #define MAS3_U0 0x00000200
81 #define MAS3_U1 0x00000100
82 #define MAS3_U2 0x00000080
83 #define MAS3_U3 0x00000040
84 #define MAS3_UX 0x00000020
85 #define MAS3_SX 0x00000010
86 #define MAS3_UW 0x00000008
87 #define MAS3_SW 0x00000004
88 #define MAS3_UR 0x00000002
89 #define MAS3_SR 0x00000001
90 #define MAS3_BAP_MASK 0x0000003f
91 #define MAS3_SPSIZE 0x0000003e
96 #define MAS4_INDD 0x00008000 /* Default IND */
98 #define MAS4_X0D 0x00000040
99 #define MAS4_X1D 0x00000020
100 #define MAS4_WD 0x00000010
101 #define MAS4_ID 0x00000008
102 #define MAS4_MD 0x00000004
103 #define MAS4_GD 0x00000002
104 #define MAS4_ED 0x00000001
105 #define MAS4_WIMGED_MASK 0x0000001f /* Default WIMGE */
106 #define MAS4_WIMGED_SHIFT 0
108 #define MAS4_ACMD 0x000000c0 /* Default ACM */
110 #define MAS4_TSIZED_MASK 0x00000f80 /* Default TSIZE */
113 #define MAS5_SGS 0x80000000
115 #define MAS6_SPID0 0x3FFF0000
116 #define MAS6_SPID1 0x00007FFE
118 #define MAS6_SAS 0x00000001
120 #define MAS6_SIND 0x00000002 /* Indirect page */
122 #define MAS6_SPID_MASK 0x3fff0000
124 #define MAS6_ISIZE_MASK 0x00000f80
127 #define MAS7_RPN 0xFFFFFFFF
129 #define MAS8_TGS 0x80000000 /* Guest space */
130 #define MAS8_VF 0x40000000 /* Virtualization Fault */
131 #define MAS8_TLPID 0x000000ff
134 #define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */
135 #define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */
136 #define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */
137 #define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */
138 #define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */
139 #define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */
140 #define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */
141 #define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */
142 #define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */
145 #define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */
146 #define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */
147 #define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */
148 #define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */
151 #define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */
152 #define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */
153 #define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */
154 #define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */
157 #define MMUCFG_MAVN_NASK 0x00000003
158 #define MMUCFG_MAVN_V1_0 0x00000000
159 #define MMUCFG_MAVN_V2_0 0x00000001
160 #define MMUCFG_NTLB_MASK 0x0000000c
162 #define MMUCFG_PIDSIZE_MASK 0x000007c0
164 #define MMUCFG_TWC 0x00008000
165 #define MMUCFG_LRAT 0x00010000
166 #define MMUCFG_RASIZE_MASK 0x00fe0000
168 #define MMUCFG_LPIDSIZE_MASK 0x0f000000
172 #define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */
173 #define TLBnCFG_HES 0x00002000 /* HW select supported */
174 #define TLBnCFG_IPROT 0x00008000 /* IPROT supported */
175 #define TLBnCFG_GTWE 0x00010000 /* Guest can write */
176 #define TLBnCFG_IND 0x00020000 /* IND entries supported */
177 #define TLBnCFG_PT 0x00040000 /* Can load from page table */
178 #define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */
180 #define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */
182 #define TLBnCFG_ASSOC 0xff000000 /* Associativity */
186 #define TLBnPS_4K 0x00000004
187 #define TLBnPS_8K 0x00000008
188 #define TLBnPS_16K 0x00000010
189 #define TLBnPS_32K 0x00000020
190 #define TLBnPS_64K 0x00000040
191 #define TLBnPS_128K 0x00000080
192 #define TLBnPS_256K 0x00000100
193 #define TLBnPS_512K 0x00000200
194 #define TLBnPS_1M 0x00000400
195 #define TLBnPS_2M 0x00000800
196 #define TLBnPS_4M 0x00001000
197 #define TLBnPS_8M 0x00002000
198 #define TLBnPS_16M 0x00004000
199 #define TLBnPS_32M 0x00008000
200 #define TLBnPS_64M 0x00010000
201 #define TLBnPS_128M 0x00020000
202 #define TLBnPS_256M 0x00040000
203 #define TLBnPS_512M 0x00080000
204 #define TLBnPS_1G 0x00100000
205 #define TLBnPS_2G 0x00200000
206 #define TLBnPS_4G 0x00400000
207 #define TLBnPS_8G 0x00800000
208 #define TLBnPS_16G 0x01000000
209 #define TLBnPS_32G 0x02000000
210 #define TLBnPS_64G 0x04000000
211 #define TLBnPS_128G 0x08000000
212 #define TLBnPS_256G 0x10000000
215 #define TLBILX_T_ALL 0
230 #define MAS2_M_IF_NEEDED 0
253 #define MMU_PAGE_SIZE_DIRECT 0x1 /* Supported as a direct size */
254 #define MMU_PAGE_SIZE_INDIRECT 0x2 /* Supported as an indirect size */
262 for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) in shift_to_mmu_psize()
302 #define PPC_HTW_NONE 0