Lines Matching +full:0 +full:x0000000c

16 #define MI_GPM		0x80000000	/* Set domain manager mode */
17 #define MI_PPM		0x40000000	/* Set subpage protection */
18 #define MI_CIDEF	0x20000000	/* Set cache inhibit when MMU dis */
19 #define MI_RSV4I	0x08000000	/* Reserve 4 TLB entries */
20 #define MI_PPCS		0x02000000	/* Use MI_RPN prob/priv state */
21 #define MI_IDXMASK	0x00001f00	/* TLB index to be loaded */
24  * Ks = 0, Kp = 1.
27 #define MI_Ks		0x80000000	/* Should not be set */
28 #define MI_Kp		0x40000000	/* Should always be set */
39  * 0 => Kernel => 11 (all accesses performed according as user iaw page definition)
45 #define MI_APG_INIT	0xde000000
52 #define MI_EPNMASK	0xfffff000	/* Effective page number for entry */
53 #define MI_EVALID	0x00000200	/* Entry is valid */
54 #define MI_ASIDMASK	0x0000000f	/* ASID match value */
62 #define MI_APG		0x000001e0	/* Access protection group (0) */
63 #define MI_GUARDED	0x00000010	/* Guarded storage */
64 #define MI_PSMASK	0x0000000c	/* Mask of page size bits */
65 #define MI_PS8MEG	0x0000000c	/* 8M page size */
66 #define MI_PS512K	0x00000004	/* 512K page size */
67 #define MI_PS4K_16K	0x00000000	/* 4K or 16K page size */
68 #define MI_SVALID	0x00000001	/* Segment entry is valid */
76 #define MI_SPS16K	0x00000008	/* Small page size (0 = 4k, 1 = 16k) */
79  * pages for boot initialization.  This has real page number of 0,
83 #define MI_BOOTINIT	0x000001fd
86 #define MD_GPM		0x80000000	/* Set domain manager mode */
87 #define MD_PPM		0x40000000	/* Set subpage protection */
88 #define MD_CIDEF	0x20000000	/* Set cache inhibit when MMU dis */
89 #define MD_WTDEF	0x10000000	/* Set writethrough when MMU dis */
90 #define MD_RSV4I	0x08000000	/* Reserve 4 TLB entries */
91 #define MD_TWAM		0x04000000	/* Use 4K page hardware assist */
92 #define MD_PPCS		0x02000000	/* Use MI_RPN prob/priv state */
93 #define MD_IDXMASK	0x00001f00	/* TLB index to be loaded */
96 #define MC_ASIDMASK	0x0000000f	/* Bits used for ASID value */
100  * Ks = 0, Kp = 1.
103 #define MD_Ks		0x80000000	/* Should not be set */
104 #define MD_Kp		0x40000000	/* Should always be set */
107 #define MD_APG_INIT	0xdc000000
108 #define MD_APG_KUAP	0xde000000
115 #define MD_EPNMASK	0xfffff000	/* Effective page number for entry */
116 #define MD_EVALID	0x00000200	/* Entry is valid */
117 #define MD_ASIDMASK	0x0000000f	/* ASID match value */
125 #define	M_L1TB		0xfffff000	/* Level 1 table base address */
126 #define M_L1INDX	0x00000ffc	/* Level 1 index, when read */
135 #define MD_L2TB		0xfffff000	/* Level 2 table base address */
136 #define MD_L2INDX	0xfffffe00	/* Level 2 index (*pte), when read */
137 #define MD_APG		0x000001e0	/* Access protection group (0) */
138 #define MD_GUARDED	0x00000010	/* Guarded storage */
139 #define MD_PSMASK	0x0000000c	/* Mask of page size bits */
140 #define MD_PS8MEG	0x0000000c	/* 8M page size */
141 #define MD_PS512K	0x00000004	/* 512K page size */
142 #define MD_PS4K_16K	0x00000000	/* 4K or 16K page size */
143 #define MD_WT		0x00000002	/* Use writethrough page attribute */
144 #define MD_SVALID	0x00000001	/* Segment entry is valid */
153 #define MD_SPS16K	0x00000008	/* Small page size (0 = 4k, 1 = 16k) */
191 #define PHYS_IMMR_BASE (mfspr(SPRN_IMMR) & 0xfff80000)
209 	for (psize = 0; psize < MMU_PAGE_COUNT; ++psize)  in shift_to_mmu_psize()