Lines Matching +full:use +full:- +full:broken +full:- +full:interrupts

1 /* SPDX-License-Identifier: GPL-2.0 */
27  *	0b00 = pass through (interrupts routed to IRQ0)
71  * Per-Processor registers
92  * Per-source registers
149  * Per-Processor registers
162  * Per-source registers
287 	/* vector numbers used for FSL MPIC error interrupts */
355 /* Set this for a big-endian MPIC */
357 /* Broken U3 MPIC */
359 /* Broken IPI registers (autodetected) */
367 /* MPIC has 11-bit vector fields (or larger) */
369 /* Enable delivery of prio 15 interrupts as MCK instead of EE */
371 /* Disable bias among target selection, spread interrupts evenly */
375 /* Enable CoreInt delivery of interrupts */
406  * for the range if interrupts passed in. No HW initialization is
411  * @isu_size:	number of interrupts in an ISU. Use 0 to use a
412  *              standard ISU-less setup (aka powermac)
414  * @irq_count:  number of irqs to use with this mpic IRQ sources. Pass 0
421  * Note about the sense array. If none is passed, all interrupts are
462 /* Setup a non-boot CPU */