Lines Matching +full:0 +full:x28000

30     char Pad1[0x30];
34     char Pad2[0x7fc4];
36     char SCSI_DMA[0x100];
37     char Pad3[0x300];
38     char SCCA_Tx_DMA[0x100];
39     char SCCA_Rx_DMA[0x100];
40     char SCCB_Tx_DMA[0x100];
41     char SCCB_Rx_DMA[0x100];
42     char Pad4[0x7800];
44     char SCSI[0x1000];
45     char ADB[0x1000];
46     char SCC_Legacy[0x1000];
47     char SCC[0x1000];
48     char Pad9[0x2000];
49     char VIA[0x2000];
50     char Pad10[0x28000];
51     char OpenPIC[0x40000];
61 #define HYDRA_FC_SCC_CELL_EN	0x00000001	/* Enable SCC Clock */
62 #define HYDRA_FC_SCSI_CELL_EN	0x00000002	/* Enable SCSI Clock */
63 #define HYDRA_FC_SCCA_ENABLE	0x00000004	/* Enable SCC A Lines */
64 #define HYDRA_FC_SCCB_ENABLE	0x00000008	/* Enable SCC B Lines */
65 #define HYDRA_FC_ARB_BYPASS	0x00000010	/* Bypass Internal Arbiter */
66 #define HYDRA_FC_RESET_SCC	0x00000020	/* Reset SCC */
67 #define HYDRA_FC_MPIC_ENABLE	0x00000040	/* Enable OpenPIC */
68 #define HYDRA_FC_SLOW_SCC_PCLK	0x00000080	/* 1=15.6672, 0=25 MHz */
69 #define HYDRA_FC_MPIC_IS_MASTER	0x00000100	/* OpenPIC Master Mode */
76 #define HYDRA_INT_SIO		0