Lines Matching +full:0 +full:xf0ffffff
14 #define BL_128K 0x000
15 #define BL_256K 0x001
16 #define BL_512K 0x003
17 #define BL_1M 0x007
18 #define BL_2M 0x00F
19 #define BL_4M 0x01F
20 #define BL_8M 0x03F
21 #define BL_16M 0x07F
22 #define BL_32M 0x0FF
23 #define BL_64M 0x1FF
24 #define BL_128M 0x3FF
25 #define BL_256M 0x7FF
28 #define BPP_XX 0x00 /* No access */
29 #define BPP_RX 0x01 /* Read only */
30 #define BPP_RW 0x02 /* Read/write */
35 #define BAT_PHYS_ADDR(x) ((u32)((x & 0x00000000fffe0000ULL) | \
36 ((x & 0x0000000e00000000ULL) >> 24) | \
37 ((x & 0x0000000100000000ULL) >> 30)))
38 #define PHYS_BAT_ADDR(x) (((u64)(x) & 0x00000000fffe0000ULL) | \
39 (((u64)(x) << 24) & 0x0000000e00000000ULL) | \
40 (((u64)(x) << 30) & 0x0000000100000000ULL))
43 #define PHYS_BAT_ADDR(x) ((x) & 0xfffe0000)
56 /* Values for PP (assumes Ks=0, Kp=1) */
57 #define PP_RWXX 0 /* Supervisor read/write, User none */
63 #define SR_NX 0x10000000 /* No Execute */
64 #define SR_KP 0x20000000 /* User key */
65 #define SR_KS 0x40000000 /* Supervisor key */
100 uus_addi 1, \tmp2, \tmp1, 0x111
101 uus_addi 2, \tmp3, \tmp1, 0x222
102 uus_addi 3, \tmp4, \tmp1, 0x333
104 uus_mtsr 0, \tmp1
109 uus_addi 4, \tmp1, \tmp1, 0x444
110 uus_addi 5, \tmp2, \tmp2, 0x444
111 uus_addi 6, \tmp3, \tmp3, 0x444
112 uus_addi 7, \tmp4, \tmp4, 0x444
119 uus_addi 8, \tmp1, \tmp1, 0x444
120 uus_addi 9, \tmp2, \tmp2, 0x444
121 uus_addi 10, \tmp3, \tmp3, 0x444
122 uus_addi 11, \tmp4, \tmp4, 0x444
129 uus_addi 12, \tmp1, \tmp1, 0x444
130 uus_addi 13, \tmp2, \tmp2, 0x444
131 uus_addi 14, \tmp3, \tmp3, 0x444
132 uus_addi 15, \tmp4, \tmp4, 0x444
152 #define CTX_TO_VSID(c, id) ((((c) * (897 * 16)) + (id * 0x111)) & 0xffffff)
165 unsigned long xpn:3; /* Real page number bits 0-2, optional */
201 mtsr(val + n * 0x111, n << 28); in update_user_segment()
206 val &= 0xf0ffffff; in update_user_segments()
208 update_user_segment(0, val); in update_user_segments()