Lines Matching +full:7 +full:- +full:31
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
10 # Poly1305 - this version mainly using vector/VSX/Scalar
11 # - 26 bits limbs
12 # - Handle multiple 64 byte blcok.
17 # p = 2^130 - 5
25 # 07/22/21 - this revison based on the above sum of products. Setup r^4, r^3, r^2, r and s3, s2, …
56 #include <asm/asm-offsets.h>
57 #include <asm/asm-compat.h>
95 stdu 1,-752(1)
114 SAVE_GPR 31, 248, 1
128 SAVE_VRS 31, 176, 9
147 SAVE_VSX 31, 464, 9
163 RESTORE_VRS 31, 176, 9
182 RESTORE_VSX 31, 464, 9
201 RESTORE_GPR 31, 248, 1
223 vmulouw 12, 7, 1
234 vmulouw 12, 7, 2
243 vmulouw 12, 7, 3
252 vmulouw 12, 7, 26
261 vmulouw 12, 7, 27
271 vmuleuw 12, 7, 1
282 vmuleuw 12, 7, 2
293 vmuleuw 12, 7, 3
304 vmuleuw 12, 7, 26
315 vmuleuw 12, 7, 27
354 xxlxor 31, 31, 31
361 vmr 7, 29
388 vmrgow 29, 29, 7
408 xxlor 7, 34, 34
443 vsrd 10, 14, 31
444 vsrd 11, 17, 31
445 vand 7, 17, 25
448 vsrd 12, 18, 31
451 vsrd 11, 15, 31
458 vsrd 13, 6, 31
461 vsrd 10, 4, 31
462 vaddudm 7, 7, 13
464 vsrd 11, 7, 31
465 vand 7, 7, 25
486 lvx 25, 0, 10 # v25 - mask
487 lvx 31, 14, 10 # v31 = 1a
571 vsrd 10, 14, 31 # >> 26
572 vsrd 11, 10, 31 # 12 bits left
581 vsrd 13, 12, 31 # >> 26, a4
587 vaddudm 23, 7, 12
598 vsrd 10, 14, 31 # >> 26
599 vsrd 11, 10, 31 # 12 bits left
608 vsrd 13, 12, 31 # >> 26, a4
615 vmrgow 7, 12, 23
619 addi 5, 5, -64 # len -= 64
623 divdu 31, 5, 9
625 cmpdi 31, 0
628 mtctr 31
633 # h3 = (h1 + m3) * r^2, h4 = (h2 + m4) * r^2 --> (h0 + m1) r*4 + (h3 + m3) r^2, (h0 + m2) r^4 + (h…
635 # h5 = (h3 + m5) * r^2, h6 = (h4 + m6) * r^2 -->
636 # h7 = (h5 + m7) * r^2, h8 = (h6 + m8) * r^1 --> m5 * r^4 + m6 * r^3 + m7 * r^2 + m8 * r
645 vsrd 10, 14, 31
646 vsrd 11, 17, 31
647 vand 7, 17, 25
650 vsrd 12, 18, 31
653 vsrd 11, 15, 31
660 vsrd 13, 6, 31
663 vsrd 10, 4, 31
664 vaddudm 7, 7, 13
666 vsrd 11, 7, 31
667 vand 7, 7, 25
690 vsrd 21, 14, 31 # >> 26
691 vsrd 22, 21, 31 # 12 bits left
692 vsrd 10, 17, 31 # >> 26
693 vsrd 11, 10, 31 # 12 bits left
709 vsrd 24, 23, 31 # >> 26, a4
712 vsrd 13, 12, 31 # >> 26, a4
718 vaddudm 7, 7, 23
725 vmrgow 7, 12, 7
729 addi 5, 5, -64 # len -= 64
742 xxlor 34, 7, 7
750 xxpermdi 41, 31, 46, 0
751 xxpermdi 42, 31, 47, 0
753 xxpermdi 36, 31, 36, 3
755 xxpermdi 37, 31, 37, 3
756 xxpermdi 43, 31, 48, 0
758 xxpermdi 38, 31, 38, 3
759 xxpermdi 44, 31, 49, 0
760 vaddudm 7, 17, 12
761 xxpermdi 39, 31, 39, 3
762 xxpermdi 45, 31, 50, 0
764 xxpermdi 40, 31, 40, 3
768 vsrd 10, 4, 31
769 vsrd 11, 7, 31
770 vand 7, 7, 25
773 vsrd 12, 8, 31
776 vsrd 11, 5, 31
783 vsrd 13, 6, 31
786 vsrd 10, 4, 31
787 vaddudm 7, 7, 13
789 vsrd 11, 7, 31
790 vand 7, 7, 25
793 vsrd 10, 5, 31
803 vsld 5, 5, 31
807 vsld 6, 6, 31
808 vsld 6, 6, 31
811 vsld 7, 7, 11
812 vor 21, 7, 12
815 vsld 8, 8, 31
857 add 19, 21, 10 # s1: r19 - (r1 >> 2) *5
878 vmsumudm 7, 6, 0, 9 # h0 * r0, h1 * s1
897 mfvsrld 27, 32+7
900 mfvsrd 20, 32+7 # h0.h
923 # - no highbit if final leftover block (highbit = 0)
931 stdu 1,-400(1)
950 SAVE_GPR 31, 248, 1
966 divdu 31, 5, 30
968 mtctr 31
1016 RESTORE_GPR 31, 248, 1
1039 # h + 5 + (-p)
1041 mr 7, 11
1044 addze 7, 7
1050 mr 11, 7
1055 ld 7, 8(4)
1057 adde 11, 11, 7