Lines Matching +full:6 +full:- +full:14
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
10 # Poly1305 - this version mainly using vector/VSX/Scalar
11 # - 26 bits limbs
12 # - Handle multiple 64 byte blcok.
17 # p = 2^130 - 5
25 # 07/22/21 - this revison based on the above sum of products. Setup r^4, r^3, r^2, r and s3, s2, …
56 #include <asm/asm-offsets.h>
57 #include <asm/asm-compat.h>
95 stdu 1,-752(1)
97 SAVE_GPR 14, 112, 1
130 SAVE_VSX 14, 192, 9
165 RESTORE_VSX 14, 192, 9
184 RESTORE_GPR 14, 112, 1
220 vmulouw 14, 4, 26
222 vmulouw 11, 6, 2
226 vaddudm 14, 14, 10
227 vaddudm 14, 14, 11
229 vmulouw 11, 6, 3
230 vaddudm 14, 14, 12
231 vaddudm 14, 14, 13 # x0
240 vmulouw 11, 6, 26
249 vmulouw 11, 6, 27
258 vmulouw 11, 6, 28
270 vmuleuw 11, 6, 2
273 vaddudm 14, 14, 9
274 vaddudm 14, 14, 10
275 vaddudm 14, 14, 11
276 vaddudm 14, 14, 12
277 vaddudm 14, 14, 13 # x0
281 vmuleuw 11, 6, 3
292 vmuleuw 11, 6, 26
303 vmuleuw 11, 6, 27
314 vmuleuw 11, 6, 28
360 vmr 6, 28
387 vmrgow 28, 28, 6
407 xxlor 6, 33, 33
443 vsrd 10, 14, 31
446 vand 4, 14, 25
456 vaddudm 6, 16, 11
458 vsrd 13, 6, 31
459 vand 6, 6, 25
482 li 14, 16
486 lvx 25, 0, 10 # v25 - mask
487 lvx 31, 14, 10 # v31 = 1a
500 extrdi 14, 9, 26, 38
503 mtvsrdd 58, 0, 14
504 insrdi 16, 10, 14, 38
548 extrdi 14, 9, 26, 38
551 mtvsrdd 36, 0, 14
552 insrdi 16, 10, 14, 38
568 vperm 14, 11, 12, 17
570 vand 9, 14, 25 # a0
571 vsrd 10, 14, 31 # >> 26
579 vspltisb 13, 14
580 vsrd 12, 15, 13 # >> 14
586 vaddudm 22, 6, 11
595 vperm 14, 11, 12, 17
597 vand 9, 14, 25 # a0
598 vsrd 10, 14, 31 # >> 26
604 vspltisb 13, 14
607 vsrd 12, 15, 13 # >> 14
614 vmrgow 6, 11, 22
619 addi 5, 5, -64 # len -= 64
633 # h3 = (h1 + m3) * r^2, h4 = (h2 + m4) * r^2 --> (h0 + m1) r*4 + (h3 + m3) r^2, (h0 + m2) r^4 + (h…
635 # h5 = (h3 + m5) * r^2, h6 = (h4 + m6) * r^2 -->
636 # h7 = (h5 + m7) * r^2, h8 = (h6 + m8) * r^1 --> m5 * r^4 + m6 * r^3 + m7 * r^2 + m8 * r
645 vsrd 10, 14, 31
648 vand 4, 14, 25
658 vaddudm 6, 16, 11
660 vsrd 13, 6, 31
661 vand 6, 6, 25
679 vperm 14, 11, 12, 17
688 vand 20, 14, 25 # a0
690 vsrd 21, 14, 31 # >> 26
707 vspltisb 13, 14
708 vsrd 23, 15, 13 # >> 14
711 vsrd 12, 18, 13 # >> 14
717 vaddudm 6, 6, 22
724 vmrgow 6, 11, 6
729 addi 5, 5, -64 # len -= 64
741 xxlor 33, 6, 6
752 vaddudm 4, 14, 9
757 vaddudm 6, 16, 11
781 vaddudm 6, 6, 11
783 vsrd 13, 6, 31
784 vand 6, 6, 25
795 vaddudm 6, 6, 10
806 vsrd 12, 6, 11
807 vsld 6, 6, 31
808 vsld 6, 6, 31
809 vor 20, 20, 6
810 vspltisb 11, 14
857 add 19, 21, 10 # s1: r19 - (r1 >> 2) *5
878 vmsumudm 7, 6, 0, 9 # h0 * r0, h1 * s1
881 vmsumudm 11, 6, 1, 9 # h0 * r1, h1 * r0
923 # - no highbit if final leftover block (highbit = 0)
931 stdu 1,-400(1)
933 SAVE_GPR 14, 112, 1
970 mr 24, 6 # highbit
984 mtvsrdd 32+6, 27, 28 # h0, h1
999 RESTORE_GPR 14, 112, 1
1039 # h + 5 + (-p)
1040 mr 6, 10
1043 addic. 6, 6, 5
1049 mr 10, 6
1054 ld 6, 0(4)
1056 addc 10, 10, 6