Lines Matching +full:10 +full:- +full:11
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
10 # Poly1305 - this version mainly using vector/VSX/Scalar
11 # - 26 bits limbs
12 # - Handle multiple 64 byte blcok.
17 # p = 2^130 - 5
25 # 07/22/21 - this revison based on the above sum of products. Setup r^4, r^3, r^2, r and s3, s2, …
56 #include <asm/asm-offsets.h>
57 #include <asm/asm-compat.h>
95 stdu 1,-752(1)
221 vmulouw 10, 5, 3
222 vmulouw 11, 6, 2
226 vaddudm 14, 14, 10
227 vaddudm 14, 14, 11
228 vmulouw 10, 5, 26
229 vmulouw 11, 6, 3
232 vaddudm 15, 15, 10
233 vaddudm 15, 15, 11
239 vmulouw 10, 5, 27
240 vmulouw 11, 6, 26
241 vaddudm 16, 16, 10
242 vaddudm 16, 16, 11
248 vmulouw 10, 5, 28
249 vmulouw 11, 6, 27
250 vaddudm 17, 17, 10
251 vaddudm 17, 17, 11
257 vmulouw 10, 5, 29
258 vmulouw 11, 6, 28
259 vaddudm 18, 18, 10
260 vaddudm 18, 18, 11
269 vmuleuw 10, 5, 3
270 vmuleuw 11, 6, 2
274 vaddudm 14, 14, 10
275 vaddudm 14, 14, 11
280 vmuleuw 10, 5, 26
281 vmuleuw 11, 6, 3
285 vaddudm 15, 15, 10
286 vaddudm 15, 15, 11
291 vmuleuw 10, 5, 27
292 vmuleuw 11, 6, 26
296 vaddudm 16, 16, 10
297 vaddudm 16, 16, 11
302 vmuleuw 10, 5, 28
303 vmuleuw 11, 6, 27
307 vaddudm 17, 17, 10
308 vaddudm 17, 17, 11
313 vmuleuw 10, 5, 29
314 vmuleuw 11, 6, 28
318 vaddudm 18, 18, 10
319 vaddudm 18, 18, 11
376 vsld 10, 28, 13
377 vsld 11, 29, 13
380 vaddudm 1, 10, 28
381 vaddudm 2, 11, 29
392 vsld 10, 28, 13
393 vsld 11, 29, 13
396 vaddudm 1, 10, 28
397 vaddudm 2, 11, 29
412 vspltw 10, 26, 2
413 vmrgow 26, 10, 9
415 vspltw 10, 27, 2
416 vmrgow 27, 10, 9
418 vspltw 10, 28, 2
419 vmrgow 28, 10, 9
421 vspltw 10, 29, 2
422 vmrgow 29, 10, 9
424 vspltw 10, 30, 2
425 vmrgow 30, 10, 9
428 vsld 10, 28, 13
429 vsld 11, 29, 13
432 vaddudm 1, 10, 28
433 vaddudm 2, 11, 29
443 vsrd 10, 14, 31
444 vsrd 11, 17, 31
447 vaddudm 18, 18, 11
449 vaddudm 15, 15, 10
451 vsrd 11, 15, 31
455 vsld 10, 12, 9
456 vaddudm 6, 16, 11
460 vaddudm 4, 4, 10
461 vsrd 10, 4, 31
464 vsrd 11, 7, 31
467 vaddudm 5, 5, 10
468 vaddudm 8, 8, 11
476 addis 10, 2, rmask@toc@ha
477 addi 10, 10, rmask@toc@l
479 ld 11, 0(10)
480 ld 12, 8(10)
484 addis 10, 2, cnum@toc@ha
485 addi 10, 10, cnum@toc@l
486 lvx 25, 0, 10 # v25 - mask
487 lvx 31, 14, 10 # v31 = 1a
488 lvx 19, 15, 10 # v19 = 1 << 24
489 lxv 24, 48(10) # vs24
490 lxv 25, 64(10) # vs25
495 ld 10, 32(3)
496 and. 9, 9, 11
497 and. 10, 10, 12
504 insrdi 16, 10, 14, 38
506 extrdi 17, 10, 26, 24
508 extrdi 18, 10, 24, 0
544 ld 10, 8(3)
552 insrdi 16, 10, 14, 38
554 extrdi 17, 10, 26, 24
556 extrdi 18, 10, 24, 0
568 vperm 14, 11, 12, 17
569 vperm 15, 11, 12, 18
571 vsrd 10, 14, 31 # >> 26
572 vsrd 11, 10, 31 # 12 bits left
573 vand 10, 10, 25 # a1
577 vor 11, 11, 12
578 vand 11, 11, 25 # a2
585 vaddudm 21, 5, 10
586 vaddudm 22, 6, 11
595 vperm 14, 11, 12, 17
596 vperm 15, 11, 12, 18
598 vsrd 10, 14, 31 # >> 26
599 vsrd 11, 10, 31 # 12 bits left
600 vand 10, 10, 25 # a1
605 vor 11, 11, 12
606 vand 11, 11, 25 # a2
613 vmrgow 5, 10, 21
614 vmrgow 6, 11, 22
619 addi 5, 5, -64 # len -= 64
633 # h3 = (h1 + m3) * r^2, h4 = (h2 + m4) * r^2 --> (h0 + m1) r*4 + (h3 + m3) r^2, (h0 + m2) r^4 + (h…
635 # h5 = (h3 + m5) * r^2, h6 = (h4 + m6) * r^2 -->
636 # h7 = (h5 + m7) * r^2, h8 = (h6 + m8) * r^1 --> m5 * r^4 + m6 * r^3 + m7 * r^2 + m8 * r
645 vsrd 10, 14, 31
646 vsrd 11, 17, 31
649 vaddudm 18, 18, 11
651 vaddudm 15, 15, 10
653 vsrd 11, 15, 31
657 vsld 10, 12, 9
658 vaddudm 6, 16, 11
662 vaddudm 4, 4, 10
663 vsrd 10, 4, 31
666 vsrd 11, 7, 31
669 vaddudm 5, 5, 10
670 vaddudm 8, 8, 11
679 vperm 14, 11, 12, 17
680 vperm 15, 11, 12, 18
685 vperm 17, 11, 12, 17
686 vperm 18, 11, 12, 18
692 vsrd 10, 17, 31 # >> 26
693 vsrd 11, 10, 31 # 12 bits left
696 vand 10, 10, 25 # a1
705 vor 11, 11, 12
706 vand 11, 11, 25 # a2
723 vmrgow 5, 10, 5
724 vmrgow 6, 11, 6
729 addi 5, 5, -64 # len -= 64
754 vaddudm 5, 15, 10
757 vaddudm 6, 16, 11
768 vsrd 10, 4, 31
769 vsrd 11, 7, 31
772 vaddudm 8, 8, 11
774 vaddudm 5, 5, 10
776 vsrd 11, 5, 31
780 vsld 10, 12, 9
781 vaddudm 6, 6, 11
785 vaddudm 4, 4, 10
786 vsrd 10, 4, 31
789 vsrd 11, 7, 31
792 vaddudm 5, 5, 10
793 vsrd 10, 5, 31
795 vaddudm 6, 6, 10
796 vaddudm 8, 8, 11
805 vspltisb 11, 12
806 vsrd 12, 6, 11
810 vspltisb 11, 14
811 vsld 7, 7, 11
814 vsld 8, 8, 11
844 addis 10, 2, rmask@toc@ha
845 addi 10, 10, rmask@toc@l
846 ld 11, 0(10)
847 ld 12, 8(10)
852 ld 10, 32(3)
853 and. 9, 9, 11 # cramp mask r0
854 and. 10, 10, 12 # cramp mask r1
856 srdi 21, 10, 2
857 add 19, 21, 10 # s1: r19 - (r1 >> 2) *5
862 mtvsrdd 32+1, 10, 9 # r1, r0
881 vmsumudm 11, 6, 1, 9 # h0 * r1, h1 * r0
882 vmsumudm 10, 8, 2, 11 # d1 += h2 * s1
885 vmsumudm 11, 8, 3, 9 # d2 = h2 * r0
898 mfvsrld 28, 32+10
899 mfvsrld 29, 32+11
901 mfvsrd 21, 32+10 # h1.h
923 # - no highbit if final leftover block (highbit = 0)
931 stdu 1,-400(1)
957 add 11, 25, 4
975 ld 20, 0(11)
976 ld 21, 8(11)
977 addi 11, 11, 16
1034 ld 10, 0(3)
1035 ld 11, 8(3)
1039 # h + 5 + (-p)
1040 mr 6, 10
1041 mr 7, 11
1049 mr 10, 6
1050 mr 11, 7
1056 addc 10, 10, 6
1057 adde 11, 11, 7
1060 std 10, 0(5)
1061 std 11, 8(5)