Lines Matching +full:0 +full:- +full:15
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
43 #include <asm/asm-offsets.h>
44 #include <asm/asm-compat.h>
79 mflr 0
80 std 0, 16(1)
81 stdu 1,-752(1)
84 SAVE_GPR 15, 120, 1
103 SAVE_VRS 20, 0, 9
117 SAVE_VSX 15, 208, 9
138 RESTORE_VRS 20, 0, 9
152 RESTORE_VSX 15, 208, 9
171 RESTORE_GPR 15, 120, 1
190 ld 0, 16(1)
191 mtlr 0
196 xxlor 0, 32+25, 32+25
198 vadduwm 0, 0, 4
207 vpermxor 12, 12, 0, 25
210 vpermxor 15, 15, 3, 25
215 xxlor 32+25, 0, 0
219 vadduwm 11, 11, 15
233 xxlor 0, 32+25, 32+25
243 xxlor 32+25, 0, 0
244 vadduwm 0, 0, 4
253 xxlor 0, 32+25, 32+25
255 vpermxor 12, 12, 0, 25
258 vpermxor 15, 15, 3, 25
263 xxlor 32+25, 0, 0
267 vadduwm 11, 11, 15
272 xxlor 0, 32+28, 32+28
290 xxlor 32+28, 0, 0
293 xxlor 0, 32+25, 32+25
295 vadduwm 0, 0, 5
304 vpermxor 15, 15, 0, 25
313 xxlor 32+25, 0, 0
314 vadduwm 10, 10, 15
331 xxlor 0, 32+25, 32+25
341 xxlor 32+25, 0, 0
343 vadduwm 0, 0, 5
352 xxlor 0, 32+25, 32+25
354 vpermxor 15, 15, 0, 25
362 xxlor 32+25, 0, 0
364 vadduwm 10, 10, 15
373 xxlor 0, 32+28, 32+28
391 xxlor 32+28, 0, 0
396 vadduwm 0, 0, 4
400 vpermxor 12, 12, 0, 20
403 vpermxor 15, 15, 3, 20
407 vadduwm 11, 11, 15
416 vadduwm 0, 0, 4
420 vpermxor 12, 12, 0, 22
423 vpermxor 15, 15, 3, 22
427 vadduwm 11, 11, 15
438 vadduwm 0, 0, 5
442 vpermxor 15, 15, 0, 20
446 vadduwm 10, 10, 15
458 vadduwm 0, 0, 5
462 vpermxor 15, 15, 0, 22
466 vadduwm 10, 10, 15
486 xxpermdi 32+\a0, 10, 11, 0 # a0, a1, a2, a3
488 xxpermdi 32+\a2, 12, 13, 0 # c0, c1, c2, c3
494 vadduwm \S+0, \S+0, 16-\S
495 vadduwm \S+4, \S+4, 17-\S
496 vadduwm \S+8, \S+8, 18-\S
497 vadduwm \S+12, \S+12, 19-\S
499 vadduwm \S+1, \S+1, 16-\S
500 vadduwm \S+5, \S+5, 17-\S
501 vadduwm \S+9, \S+9, 18-\S
502 vadduwm \S+13, \S+13, 19-\S
504 vadduwm \S+2, \S+2, 16-\S
505 vadduwm \S+6, \S+6, 17-\S
506 vadduwm \S+10, \S+10, 18-\S
507 vadduwm \S+14, \S+14, 19-\S
509 vadduwm \S+3, \S+3, 16-\S
510 vadduwm \S+7, \S+7, 17-\S
511 vadduwm \S+11, \S+11, 18-\S
512 vadduwm \S+15, \S+15, 19-\S
521 lxvw4x 0, 0, 9
536 lxvw4x 15, 31, 9
538 xxlxor \S+32, \S+32, 0
553 xxlxor \S+47, \S+47, 15
555 stxvw4x \S+32, 0, 16
582 cmpdi 6, 0
587 # r17 - r31 mainly for Write_256 macro.
604 mr 15, 6 # len
605 li 14, 0 # offset to inp and outp
607 lxvw4x 48, 0, 3 # vr16, constants
612 # create (0, 1, 2, 3) counters
613 vspltisw 0, 0
617 vmrghw 4, 0, 1
619 vsldoi 30, 4, 5, 8 # vr30 counter, 4 (0, 1, 2, 3)
626 lxvw4x 32+20, 0, 11
645 vadduwm 31, 30, 25 # counter = (0, 1, 2, 3) + (4, 4, 4, 4)
658 xxspltw 32+0, 16, 0
663 xxspltw 32+4, 17, 0
667 xxspltw 32+8, 18, 0
671 xxspltw 32+12, 19, 0
674 xxspltw 32+15, 19, 3
677 xxspltw 32+16, 16, 0
682 xxspltw 32+20, 17, 0
686 xxspltw 32+24, 18, 0
690 xxspltw 32+28, 19, 0
702 xxlor 0, 32+30, 32+30
705 xxlor 32+30, 0, 0
706 TP_4x 0, 1, 2, 3
709 TP_4x 12, 13, 14, 15
711 xxlor 0, 48, 48
719 Add_state 0
720 xxlor 48, 0, 0
724 Write_256 0
726 addi 15, 15, -256 # len -=256
732 TP_4x 16+0, 16+1, 16+2, 16+3
735 TP_4x 16+12, 16+13, 16+14, 16+15
744 addi 15, 15, -256 # len +=256
754 cmpdi 15, 0
757 cmpdi 15, 512
764 lxvw4x 48, 0, 3 # vr16, constants
773 lxvw4x 32+20, 0, 11
780 vspltw 0, 16, 0
785 vspltw 4, 17, 0
789 vspltw 8, 18, 0
793 vspltw 12, 19, 0
797 vspltw 15, 19, 3
806 TP_4x 0, 1, 2, 3
809 TP_4x 12, 13, 14, 15
811 Add_state 0
812 Write_256 0
814 addi 15, 15, -256 # len += 256
820 cmpdi 15, 0
822 cmpdi 15, 256
833 li 3, 0
840 .long 0x22330011, 0x66774455, 0xaabb8899, 0xeeffccdd
841 .long 0x11223300, 0x55667744, 0x99aabb88, 0xddeeffcc