boot/dts/xpedite5330.dts

16 	boot-bank = <0x0>;	/* 0: Primary flash, 1: Secondary flash */
29 		#address-cells = <1>;
43 		#address-cells = <1>;
64 		#address-cells = <1>;
80 		PowerPC,8572@1 {
101 		#size-cells = <1>;
108 			  1 0 0 0xf0000000 0x8000000 /* CS1: Alternate flash */
116 			#address-cells = <1>;
117 			#size-cells = <1>;
122 			partition@6f00000 {
126 			partition@7f00000 {
141 		nor-alternate@1,0 {
145 			reg = <1 0 0x8000000>; /* 128MB */
146 			#address-cells = <1>;
147 			#size-cells = <1>;
152 			partition@6f00000 {
156 			partition@7f00000 {
172 			#address-cells = <1>;
173 			#size-cells = <1>;
175 			 * Actual part could be ST Micro NAND08GW3B2A (1 GB),
177 			 * MT29F16G08FAA (2x 1 GB), depending on the build
183 			/* U-Boot should fix this up if chip size > 1 GB */
193 		#address-cells = <1>;
194 		#size-cells = <1>;
231 			cache-size = <0x100000>; // L2, 1M
237 			#address-cells = <1>;
285 			gpio2: gpio@1c {
293 			gpio3: gpio@1e {
301 			gpio4: gpio@1f {
311 			#address-cells = <1>;
313 			cell-index = <1>;
322 			#address-cells = <1>;
323 			#size-cells = <1>;
327 			cell-index = <1>;
340 				cell-index = <1>;
363 			#address-cells = <1>;
364 			#size-cells = <1>;
381 				cell-index = <1>;
403 		/* eTSEC 1 */
405 			#address-cells = <1>;
406 			#size-cells = <1>;
421 				#address-cells = <1>;
426 				phy0: ethernet-phy@1 {
428 					interrupts = <8 1>;
433 					interrupts = <8 1>;
445 			#address-cells = <1>;
446 			#size-cells = <1>;
447 			cell-index = <1>;
461 				#address-cells = <1>;
486 			cell-index = <1>;
519 				     "fsl,sec2.1", "fsl,sec2.0";
552 				gpios = <&gpio0 4 1>;
558 				gpios = <&gpio0 5 1>;
563 				gpios = <&gpio0 6 1>;
568 				gpios = <&gpio0 7 1>;
599 		#interrupt-cells = <1>;
635 		#interrupt-cells = <1>;
668 	/* PCI Express controller 1, XMC P15 */
672 		#interrupt-cells = <1>;