boot/dts/xpedite5301.dts

16 	boot-bank = <0x0>;	/* 0: Primary flash, 1: Secondary flash */
28 		#address-cells = <1>;
44 		PowerPC,8572@1 {
65 		#size-cells = <1>;
72 			  1 0 0 0xf0000000 0x8000000 /* CS1: Alternate flash */
80 			#address-cells = <1>;
81 			#size-cells = <1>;
86 			partition@6f00000 {
90 			partition@7f00000 {
105 		nor-alternate@1,0 {
109 			reg = <1 0 0x8000000>; /* 128MB */
110 			#address-cells = <1>;
111 			#size-cells = <1>;
116 			partition@6f00000 {
120 			partition@7f00000 {
136 			#address-cells = <1>;
137 			#size-cells = <1>;
139 			 * Actual part could be ST Micro NAND08GW3B2A (1 GB),
141 			 * MT29F16G08FAA (2x 1 GB), depending on the build
147 			/* U-Boot should fix this up if chip size > 1 GB */
157 		#address-cells = <1>;
158 		#size-cells = <1>;
195 			cache-size = <0x100000>; // L2, 1M
201 			#address-cells = <1>;
249 			gpio2: gpio@1c {
257 			gpio3: gpio@1e {
265 			gpio4: gpio@1f {
275 			#address-cells = <1>;
277 			cell-index = <1>;
286 			#address-cells = <1>;
287 			#size-cells = <1>;
291 			cell-index = <1>;
304 				cell-index = <1>;
327 			#address-cells = <1>;
328 			#size-cells = <1>;
345 				cell-index = <1>;
367 		/* eTSEC 1 */
369 			#address-cells = <1>;
370 			#size-cells = <1>;
385 				#address-cells = <1>;
390 				phy0: ethernet-phy@1 {
392 					interrupts = <8 1>;
397 					interrupts = <8 1>;
409 			#address-cells = <1>;
410 			#size-cells = <1>;
411 			cell-index = <1>;
425 				#address-cells = <1>;
450 			cell-index = <1>;
483 				     "fsl,sec2.1", "fsl,sec2.0";
516 				gpios = <&gpio0 4 1>;
522 				gpios = <&gpio0 5 1>;
527 				gpios = <&gpio0 6 1>;
532 				gpios = <&gpio0 7 1>;
568 		#interrupt-cells = <1>;
601 	/* PCI Express controller 1, wired to PEX8112 for PMC interface */
605 		#interrupt-cells = <1>;