Lines Matching +full:1 +full:f00000
27 #address-cells = <1>;
43 PowerPC,8572@1 {
64 #size-cells = <1>;
70 ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Flash 1 */
71 1 0 0 0xf0000000 0x8000000 /* CS1: Flash 2 */
80 #address-cells = <1>;
81 #size-cells = <1>;
86 partition@6f00000 {
90 partition@7f00000 {
105 nor-alternate@1,0 {
109 reg = <1 0 0x8000000>; /* 128MB */
110 #address-cells = <1>;
111 #size-cells = <1>;
116 partition@6f00000 {
120 partition@7f00000 {
136 #address-cells = <1>;
137 #size-cells = <1>;
139 * Actual part could be ST Micro NAND08GW3B2A (1 GB),
141 * MT29F16G08FAA (2x 1 GB), depending on the build
147 /* U-Boot should fix this up if chip size > 1 GB */
159 interrupts = <10 1>;
164 #address-cells = <1>;
165 #size-cells = <1>;
202 cache-size = <0x100000>; // L2, 1M
208 #address-cells = <1>;
258 gpio2: gpio@1c {
267 gpio3: gpio@1d {
276 gpio4: gpio@1e {
285 gpio5: gpio@1f {
295 #address-cells = <1>;
297 cell-index = <1>;
306 #address-cells = <1>;
307 #size-cells = <1>;
311 cell-index = <1>;
324 cell-index = <1>;
347 #address-cells = <1>;
348 #size-cells = <1>;
365 cell-index = <1>;
387 /* eTSEC 1 front panel 0 */
389 #address-cells = <1>;
390 #size-cells = <1>;
405 #address-cells = <1>;
410 phy0: ethernet-phy@1 {
412 interrupts = <4 1>;
417 interrupts = <4 1>;
422 interrupts = <5 1>;
427 interrupts = <5 1>;
437 /* eTSEC 2 front panel 1 */
439 #address-cells = <1>;
440 #size-cells = <1>;
441 cell-index = <1>;
455 #address-cells = <1>;
469 #address-cells = <1>;
470 #size-cells = <1>;
485 #address-cells = <1>;
497 /* eTSEC 4 PICMG2.16 backplane port 1 */
499 #address-cells = <1>;
500 #size-cells = <1>;
515 #address-cells = <1>;
540 cell-index = <1>;
573 "fsl,sec2.1", "fsl,sec2.0";
606 gpios = <&gpio0 4 1>;
612 gpios = <&gpio0 5 1>;
617 gpios = <&gpio0 6 1>;
622 gpios = <&gpio0 7 1>;
657 /* PCI Express controller 1, wired to PEX8648 PCIe switch */
661 #interrupt-cells = <1>;