boot/dts/sequoia.dts

22 	dcr-parent = <&{/cpus/cpu@0}>;
35 		#size-cells = <0>;
37 		cpu@0 {
40 			reg = <0x00000000>;
41 			clock-frequency = <0>; /* Filled in by zImage */
42 			timebase-frequency = <0>; /* Filled in by zImage */
54 		reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by zImage */
60 		cell-index = <0>;
61 		dcr-reg = <0x0c0 0x009>;
62 		#address-cells = <0>;
63 		#size-cells = <0>;
71 		dcr-reg = <0x0d0 0x009>;
72 		#address-cells = <0>;
73 		#size-cells = <0>;
75 		interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
83 		dcr-reg = <0x0e0 0x009>;
84 		#address-cells = <0>;
85 		#size-cells = <0>;
87 		interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */
93 		dcr-reg = <0x00e 0x002>;
98 		dcr-reg = <0x00c 0x002>;
106 		clock-frequency = <0>; /* Filled in by zImage */
110 			dcr-reg = <0x010 0x002>;
115 			reg = <0 0xE0100000 0x80400>;
117 			interrupts = <0x17 0x4>;
122 			reg = <0 0xE0120000 0x150>;
127 			dcr-reg = <0x100 0x027>;
132 			dcr-reg = <0x180 0x062>;
136 			interrupts = <0x0 0x1 0x2 0x3 0x4>;
138 			#address-cells = <0>;
139 			#size-cells = <0>;
140 			interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
141 					/*RXEOB*/ 0x1 &UIC0 0xb 0x4
142 					/*SERR*/  0x2 &UIC1 0x0 0x4
143 					/*TXDE*/  0x3 &UIC1 0x1 0x4
144 					/*RXDE*/  0x4 &UIC1 0x2 0x4>;
145 			interrupt-map-mask = <0xffffffff>;
150 			reg = <0x00000000 0xe0000400 0x00000060>;
152 			interrupts = <0x15 0x8>;
158 			interrupts = <0x1a 0x4>;
159 			reg = <0x00000000 0xe0000300 0x00000090 0x00000000 0xe0000390 0x00000070>;
167 		  	ranges = <0x00000000 0x00000001 0x00000000 0x80000000
168 			          0x80000000 0x00000001 0x80000000 0x80000000>;
170 		  	interrupts = <0x7 0x4>;
171 		  	clock-frequency = <0>; /* Filled in by zImage */
175 				dcr-reg = <0x012 0x002>;
178 				clock-frequency = <0>; /* Filled in by zImage */
179 				interrupts = <0x5 0x1>;
182 				nor_flash@0,0 {
185 					reg = <0x00000000 0x00000000 0x04000000>;
188 					partition@0 {
190 						reg = <0x00000000 0x00180000>;
194 						reg = <0x00180000 0x00200000>;
198 						reg = <0x00380000 0x03aa0000>;
202 						reg = <0x03e20000 0x00140000>;
206 						reg = <0x03f60000 0x00040000>;
210 						reg = <0x03fa0000 0x00060000>;
214 				ndfc@3,0 {
216 					reg = <0x00000003 0x00000000 0x00002000>;
217 					ccr = <0x00001000>;
218 					bank-settings = <0x80002222>;
226 						partition@0 {
228 							reg = <0x00000000 0x00084000>;
232 							reg = <0x00084000 0x01f7c000>;
241 		   		reg = <0xef600300 0x00000008>;
242 		   		virtual-reg = <0xef600300>;
243 		   		clock-frequency = <0>; /* Filled in by zImage */
246 		   		interrupts = <0x0 0x4>;
252 		   		reg = <0xef600400 0x00000008>;
253 		   		virtual-reg = <0xef600400>;
254 		   		clock-frequency = <0>;
255 		   		current-speed = <0>;
257 		   		interrupts = <0x1 0x4>;
263 		   		reg = <0xef600500 0x00000008>;
264 		   		virtual-reg = <0xef600500>;
265 		   		clock-frequency = <0>;
266 		   		current-speed = <0>;
268 		   		interrupts = <0x3 0x4>;
274 		   		reg = <0xef600600 0x00000008>;
275 		   		virtual-reg = <0xef600600>;
276 		   		clock-frequency = <0>;
277 		   		current-speed = <0>;
279 		   		interrupts = <0x4 0x4>;
284 				#size-cells = <0>;
286 				reg = <0xef600700 0x00000014>;
288 				interrupts = <0x2 0x4>;
292 					reg = <0x48>;
298 				#size-cells = <0>;
300 				reg = <0xef600800 0x00000014>;
302 				interrupts = <0x7 0x4>;
307 				reg = <0xef600d00 0x0000000c>;
312 				reg = <0xef601000 0x00000008>;
320 				interrupts = <0x0 0x1>;
322 				#address-cells = <0>;
323 				#size-cells = <0>;
324 				interrupt-map = </*Status*/ 0x0 &UIC0 0x18 0x4
325 						/*Wake*/  0x1 &UIC1 0x1d 0x4>;
326 				reg = <0xef600e00 0x00000074>;
329 				mal-tx-channel = <0>;
330 				mal-rx-channel = <0>;
331 				cell-index = <0>;
336 				phy-map = <0x00000000>;
338 				zmii-channel = <0>;
340 				rgmii-channel = <0>;
349 				interrupts = <0x0 0x1>;
351 				#address-cells = <0>;
352 				#size-cells = <0>;
353 				interrupt-map = </*Status*/ 0x0 &UIC0 0x19 0x4
354 						/*Wake*/  0x1 &UIC1 0x1f 0x4>;
355 				reg = <0xef600f00 0x00000074>;
365 				phy-map = <0x00000000>;
382 			reg = <0x00000001 0xeec00000 0x00000008	/* Config space access */
383 			       0x00000001 0xeed00000 0x00000004	/* IACK */
384 			       0x00000001 0xeed00000 0x00000004	/* Special cycle */
385 			       0x00000001 0xef400000 0x00000040>;	/* Internal registers */
395 			ranges = <0x02000000 0x00000000 0x80000000 0x00000001 0x80000000 0x00000000 0x40000000
396 				0x01000000 0x00000000 0x00000000 0x00000001 0xe8000000 0x00000000 0x00010000
397 				0x01000000 0x00000000 0x00000000 0x00000001 0xe8800000 0x00000000 0x03800000>;
399 			/* Inbound 2GB range starting at 0 */
400 			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
403 			interrupt-map-mask = <0x0 0x0 0x0 0x0>;
404 			interrupt-map = < 0x0 0x0 0x0 0x0 &UIC2 0x3 0x8 >;