Lines Matching +full:0 +full:xf800
28 #size-cells = <0>;
30 PowerPC,8377@0 {
32 reg = <0x0>;
37 timebase-frequency = <0>;
38 bus-frequency = <0>;
39 clock-frequency = <0>;
45 reg = <0x00000000 0x20000000>; // 512MB at 0
52 reg = <0xe0005000 0x1000>;
53 interrupts = <77 0x8>;
55 ranges = <0x0 0x0 0xfc000000 0x04000000>;
57 flash@0,0 {
61 reg = <0x0 0x0 0x4000000>;
65 partition@0 {
66 reg = <0 0x80000>;
72 reg = <0xa0000 0x300000>;
77 reg = <0x3a0000 0x3c60000>;
88 ranges = <0x0 0xe0000000 0x00100000>;
89 reg = <0xe0000000 0x00000200>;
90 bus-frequency = <0>;
95 reg = <0x200 0x100>;
101 reg = <0xc00 0x100>;
102 interrupts = <74 0x8>;
110 reg = <0xd00 0x100>;
111 interrupts = <75 0x8>;
120 sleep = <&pmc 0x0c000000>;
125 #size-cells = <0>;
126 cell-index = <0>;
128 reg = <0x3000 0x100>;
129 interrupts = <14 0x8>;
135 reg = <0x50>;
140 reg = <0x68>;
146 reg = <0x2e000 0x1000>;
147 interrupts = <42 0x8>;
156 #size-cells = <0>;
159 reg = <0x3100 0x100>;
160 interrupts = <15 0x8>;
166 cell-index = <0>;
168 reg = <0x7000 0x1000>;
169 interrupts = <16 0x8>;
178 reg = <0x82a8 4>;
179 ranges = <0 0x8100 0x1a8>;
182 cell-index = <0>;
183 dma-channel@0 {
185 reg = <0 0x80>;
186 cell-index = <0>;
192 reg = <0x80 0x80>;
199 reg = <0x100 0x80>;
206 reg = <0x180 0x28>;
215 reg = <0x23000 0x1000>;
217 #size-cells = <0>;
219 interrupts = <38 0x8>;
221 sleep = <&pmc 0x00c00000>;
227 cell-index = <0>;
231 reg = <0x24000 0x1000>;
232 ranges = <0x0 0x24000 0x1000>;
234 interrupts = <32 0x8 33 0x8 34 0x8>;
239 sleep = <&pmc 0xc0000000>;
244 #size-cells = <0>;
246 reg = <0x520 0x20>;
250 interrupts = <17 0x8>;
251 reg = <0x2>;
256 interrupts = <18 0x8>;
257 reg = <0x3>;
261 reg = <0x11>;
274 reg = <0x25000 0x1000>;
275 ranges = <0x0 0x25000 0x1000>;
277 interrupts = <35 0x8 36 0x8 37 0x8>;
282 sleep = <&pmc 0x30000000>;
287 #size-cells = <0>;
289 reg = <0x520 0x20>;
292 reg = <0x11>;
299 cell-index = <0>;
302 reg = <0x4500 0x100>;
303 clock-frequency = <0>;
304 interrupts = <9 0x8>;
312 reg = <0x4600 0x100>;
313 clock-frequency = <0>;
314 interrupts = <10 0x8>;
319 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
320 "fsl,sec2.1", "fsl,sec2.0";
321 reg = <0x30000 0x10000>;
322 interrupts = <11 0x8>;
326 fsl,exec-units-mask = <0x9fe>;
327 fsl,descriptor-types-mask = <0x3ab0ebf>;
328 sleep = <&pmc 0x03000000>;
333 reg = <0x18000 0x1000>;
334 interrupts = <44 0x8>;
336 sleep = <&pmc 0x000000c0>;
341 reg = <0x19000 0x1000>;
342 interrupts = <45 0x8>;
344 sleep = <&pmc 0x00000030>;
356 #address-cells = <0>;
358 reg = <0x700 0x100>;
363 reg = <0xb00 0x100 0xa00 0x100>;
364 interrupts = <80 0x8>;
370 interrupt-map-mask = <0xf800 0 0 7>;
372 /* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */
375 0x7000 0x0 0x0 0x1 &ipic 22 0x8
378 0x7800 0x0 0x0 0x1 &ipic 21 0x8>;
380 interrupts = <66 0x8>;
381 bus-range = <0 0>;
382 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
383 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
384 0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
385 sleep = <&pmc 0x00010000>;
390 reg = <0xe0008500 0x100 /* internal registers */
391 0xe0008300 0x8>; /* config space access registers */
402 reg = <0xe0009000 0x00001000>;
403 ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
404 0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
405 bus-range = <0 255>;
406 interrupt-map-mask = <0xf800 0 0 7>;
407 interrupt-map = <0 0 0 1 &ipic 1 8
408 0 0 0 2 &ipic 1 8
409 0 0 0 3 &ipic 1 8
410 0 0 0 4 &ipic 1 8>;
411 sleep = <&pmc 0x00300000>;
412 clock-frequency = <0>;
414 pcie@0 {
418 reg = <0 0 0 0 0>;
419 ranges = <0x02000000 0 0xa8000000
420 0x02000000 0 0xa8000000
421 0 0x10000000
422 0x01000000 0 0x00000000
423 0x01000000 0 0x00000000
424 0 0x00800000>;
434 reg = <0xe000a000 0x00001000>;
435 ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
436 0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
437 bus-range = <0 255>;
438 interrupt-map-mask = <0xf800 0 0 7>;
439 interrupt-map = <0 0 0 1 &ipic 2 8
440 0 0 0 2 &ipic 2 8
441 0 0 0 3 &ipic 2 8
442 0 0 0 4 &ipic 2 8>;
443 sleep = <&pmc 0x000c0000>;
444 clock-frequency = <0>;
446 pcie@0 {
450 reg = <0 0 0 0 0>;
451 ranges = <0x02000000 0 0xc8000000
452 0x02000000 0 0xc8000000
453 0 0x10000000
454 0x01000000 0 0x00000000
455 0x01000000 0 0x00000000
456 0 0x00800000>;