Lines Matching +full:0 +full:xfa000000
27 #size-cells = <0>;
29 PowerPC,8377@0 {
31 reg = <0x0>;
36 timebase-frequency = <0>;
37 bus-frequency = <0>;
38 clock-frequency = <0>;
44 reg = <0x00000000 0x10000000>; // 256MB at 0
51 reg = <0xe0005000 0x1000>;
52 interrupts = <77 0x8>;
58 ranges = <0x0 0x0 0xfe000000 0x00800000
59 0x1 0x0 0xe0600000 0x00008000
60 0x2 0x0 0xf0000000 0x00020000
61 0x3 0x0 0xfa000000 0x00008000>;
63 flash@0,0 {
67 reg = <0x0 0x0 0x800000>;
72 nand@1,0 {
77 reg = <0x1 0x0 0x8000>;
79 u-boot@0 {
80 reg = <0x0 0x100000>;
85 reg = <0x100000 0x300000>;
88 reg = <0x400000 0x1c00000>;
98 ranges = <0x0 0xe0000000 0x00100000>;
99 reg = <0xe0000000 0x00000200>;
100 bus-frequency = <0>;
105 reg = <0x200 0x100>;
111 reg = <0xc00 0x100>;
112 interrupts = <74 0x8>;
120 reg = <0xd00 0x100>;
121 interrupts = <75 0x8>;
130 sleep = <&pmc 0x0c000000>;
135 #size-cells = <0>;
136 cell-index = <0>;
138 reg = <0x3000 0x100>;
139 interrupts = <14 0x8>;
145 reg = <0x48>;
150 reg = <0x50>;
155 reg = <0x68>;
162 reg = <0x0a>;
169 reg = <0x2e000 0x1000>;
170 interrupts = <42 0x8>;
180 #size-cells = <0>;
183 reg = <0x3100 0x100>;
184 interrupts = <15 0x8>;
190 cell-index = <0>;
192 reg = <0x7000 0x1000>;
193 interrupts = <16 0x8>;
202 reg = <0x82a8 4>;
203 ranges = <0 0x8100 0x1a8>;
206 cell-index = <0>;
207 dma-channel@0 {
209 reg = <0 0x80>;
210 cell-index = <0>;
216 reg = <0x80 0x80>;
223 reg = <0x100 0x80>;
230 reg = <0x180 0x28>;
239 reg = <0x23000 0x1000>;
241 #size-cells = <0>;
243 interrupts = <38 0x8>;
245 sleep = <&pmc 0x00c00000>;
251 cell-index = <0>;
255 reg = <0x24000 0x1000>;
256 ranges = <0x0 0x24000 0x1000>;
258 interrupts = <32 0x8 33 0x8 34 0x8>;
263 sleep = <&pmc 0xc0000000>;
268 #size-cells = <0>;
270 reg = <0x520 0x20>;
274 interrupts = <17 0x8>;
275 reg = <0x2>;
279 reg = <0x11>;
292 reg = <0x25000 0x1000>;
293 ranges = <0x0 0x25000 0x1000>;
295 interrupts = <35 0x8 36 0x8 37 0x8>;
298 fixed-link = <1 1 1000 0 0>;
300 sleep = <&pmc 0x30000000>;
305 #size-cells = <0>;
307 reg = <0x520 0x20>;
310 reg = <0x11>;
317 cell-index = <0>;
320 reg = <0x4500 0x100>;
321 clock-frequency = <0>;
322 interrupts = <9 0x8>;
330 reg = <0x4600 0x100>;
331 clock-frequency = <0>;
332 interrupts = <10 0x8>;
337 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
338 "fsl,sec2.1", "fsl,sec2.0";
339 reg = <0x30000 0x10000>;
340 interrupts = <11 0x8>;
344 fsl,exec-units-mask = <0x9fe>;
345 fsl,descriptor-types-mask = <0x3ab0ebf>;
346 sleep = <&pmc 0x03000000>;
351 reg = <0x18000 0x1000>;
352 interrupts = <44 0x8>;
354 sleep = <&pmc 0x000000c0>;
359 reg = <0x19000 0x1000>;
360 interrupts = <45 0x8>;
362 sleep = <&pmc 0x00000030>;
374 #address-cells = <0>;
376 reg = <0x700 0x100>;
381 reg = <0xb00 0x100 0xa00 0x100>;
382 interrupts = <80 0x8>;
388 interrupt-map-mask = <0xf800 0 0 7>;
390 /* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */
393 0x7000 0x0 0x0 0x1 &ipic 22 0x8
396 0x7800 0x0 0x0 0x1 &ipic 21 0x8
397 0x7800 0x0 0x0 0x2 &ipic 22 0x8
398 0x7800 0x0 0x0 0x4 &ipic 23 0x8
401 0xE000 0x0 0x0 0x1 &ipic 23 0x8
402 0xE000 0x0 0x0 0x2 &ipic 21 0x8
403 0xE000 0x0 0x0 0x3 &ipic 22 0x8>;
405 interrupts = <66 0x8>;
406 bus-range = <0 0>;
407 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
408 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
409 0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
410 sleep = <&pmc 0x00010000>;
415 reg = <0xe0008500 0x100 /* internal registers */
416 0xe0008300 0x8>; /* config space access registers */
427 reg = <0xe0009000 0x00001000>;
428 ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
429 0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
430 bus-range = <0 255>;
431 interrupt-map-mask = <0xf800 0 0 7>;
432 interrupt-map = <0 0 0 1 &ipic 1 8
433 0 0 0 2 &ipic 1 8
434 0 0 0 3 &ipic 1 8
435 0 0 0 4 &ipic 1 8>;
436 sleep = <&pmc 0x00300000>;
437 clock-frequency = <0>;
439 pcie@0 {
443 reg = <0 0 0 0 0>;
444 ranges = <0x02000000 0 0xa8000000
445 0x02000000 0 0xa8000000
446 0 0x10000000
447 0x01000000 0 0x00000000
448 0x01000000 0 0x00000000
449 0 0x00800000>;
459 reg = <0xe000a000 0x00001000>;
460 ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
461 0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
462 bus-range = <0 255>;
463 interrupt-map-mask = <0xf800 0 0 7>;
464 interrupt-map = <0 0 0 1 &ipic 2 8
465 0 0 0 2 &ipic 2 8
466 0 0 0 3 &ipic 2 8
467 0 0 0 4 &ipic 2 8>;
468 sleep = <&pmc 0x000c0000>;
469 clock-frequency = <0>;
471 pcie@0 {
475 reg = <0 0 0 0 0>;
476 ranges = <0x02000000 0 0xc8000000
477 0x02000000 0 0xc8000000
478 0 0x10000000
479 0x01000000 0 0x00000000
480 0x01000000 0 0x00000000
481 0 0x00800000>;
489 gpios = <&mcu_pio 0 0>;
494 gpios = <&mcu_pio 1 0>;