boot/dts/mpc836x_rdk.dts

32 		#size-cells = <0>;
34 		PowerPC,8360@0 {
36 			reg = <0>;
42 			timebase-frequency = <0>;
43 			bus-frequency = <0>;
44 			clock-frequency = <0>;
51 		reg = <0 0>;
60 		ranges = <0 0xe0000000 0x200000>;
61 		reg = <0xe0000000 0x200>;
63 		bus-frequency = <0>;
67 			reg = <0x200 0x100>;
72 			reg = <0xb00 0x100 0xa00 0x100>;
73 			interrupts = <80 0x8>;
79 			#size-cells = <0>;
80 			cell-index = <0>;
82 			reg = <0x3000 0x100>;
90 			#size-cells = <0>;
93 			reg = <0x3100 0x100>;
102 			reg = <0x4500 0x100>;
106 			clock-frequency = <0>;
112 			reg = <0x4600 0x100>;
116 			clock-frequency = <0>;
123 			reg = <0x82a8 4>;
124 			ranges = <0 0x8100 0x1a8>;
127 			cell-index = <0>;
128 			dma-channel@0 {
130 				reg = <0 0x80>;
131 				cell-index = <0>;
137 				reg = <0x80 0x80>;
144 				reg = <0x100 0x80>;
151 				reg = <0x180 0x28>;
159 			compatible = "fsl,sec2.0";
160 			reg = <0x30000 0x10000>;
161 			interrupts = <11 0x8>;
165 			fsl,exec-units-mask = <0x7e>;
166 			fsl,descriptor-types-mask = <0x01010ebf>;
167 			sleep = <&pmc 0x03000000>;
171 			#address-cells = <0>;
175 			reg = <0x700 0x100>;
182 			reg = <0x1418 0x18>;
190 			reg = <0x1460 0x18>;
199 			ranges = <0 0x100000 0x100000>;
200 			reg = <0x100000 0x480>;
202 			clock-frequency = <0>;
203 			bus-frequency = <0>;
204 			brg-frequency = <0>;
212 				ranges = <0 0x10000 0xc000>;
214 				data-only@0 {
217 					reg = <0 0xc000>;
224 				reg = <0x440 0x40>;
233 				reg = <0x6c0 0x40 0x8b00 0x100>;
237 				gpios = <&qe_pio_b  2 0 /* USBOE */
238 					 &qe_pio_b  3 0 /* USBTP */
239 					 &qe_pio_b  8 0 /* USBTN */
240 					 &qe_pio_b  9 0 /* USBRP */
241 					 &qe_pio_b 11 0 /* USBRN */
242 					 &qe_pio_e 20 0 /* SPEED */
247 				cell-index = <0>;
249 				reg = <0x4c0 0x40>;
258 				reg = <0x500 0x40>;
268 				reg = <0x2000 0x200>;
283 				reg = <0x3000 0x200>;
298 				reg = <0x2600 0x200>;
313 				reg = <0x3200 0x200>;
326 				#size-cells = <0>;
328 				reg = <0x2120 0x18>;
354 				reg = <0x2400 0x200>;
356 				port-number = <0>;
367 				reg = <0x3400 0x200>;
378 				#address-cells = <0>;
382 				reg = <0x80 0x80>;
395 		reg = <0xe0005000 0xd8>;
396 		ranges = <0 0 0xff800000 0x0800000
397 			  1 0 0x60000000 0x0001000
398 			  2 0 0x70000000 0x4000000>;
400 		flash@0,0 {
402 			reg = <0 0 0x800000>;
407 		upm@1,0 {
409 			reg = <1 0 1>;
412 			gpios = <&qe_pio_e 18 0>;
419 		display@2,0 {
422 			reg = <2 0 0x4000000>;
426 			address = <0>;
427 			depth = <0>;
428 			width = <0>;
429 			height = <0>;
430 			linebytes = <0>;
441 		reg = <0xe0008500 0x100		/* internal registers */
442 		       0xe0008300 0x8>;		/* config space access registers */
443 		ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
444 			  0x42000000 0 0x80000000 0x80000000 0 0x10000000
445 			  0x01000000 0 0xe0300000 0xe0300000 0 0x00100000>;
448 		interrupt-map-mask = <0xf800 0 0 7>;
449 		interrupt-map = </* miniPCI0 IDSEL 0x14 AD20 */
450 				 0xa000 0 0 1 &ipic 18 8
451 				 0xa000 0 0 2 &ipic 19 8
453 				 /* PCI1 IDSEL 0x15 AD21 */
454 				 0xa800 0 0 1 &ipic 19 8
455 				 0xa800 0 0 2 &ipic 20 8
456 				 0xa800 0 0 3 &ipic 21 8
457 				 0xa800 0 0 4 &ipic 18 8>;
458 		sleep = <&pmc 0x00010000>;
460 		bus-range = <0 0>;
461 		clock-frequency = <0>;