Lines Matching +full:0 +full:xf800
27 #size-cells = <0>;
29 PowerPC,8315@0 {
31 reg = <0x0>;
36 timebase-frequency = <0>; // from bootloader
37 bus-frequency = <0>; // from bootloader
38 clock-frequency = <0>; // from bootloader
44 reg = <0x00000000 0x08000000>; // 128MB at 0
51 reg = <0xe0005000 0x1000>;
52 interrupts = <77 0x8>;
58 ranges = <0x0 0x0 0xfe000000 0x00800000
59 0x1 0x0 0xe0600000 0x00002000
60 0x2 0x0 0xf0000000 0x00020000
61 0x3 0x0 0xfa000000 0x00008000>;
63 flash@0,0 {
67 reg = <0x0 0x0 0x800000>;
72 nand@1,0 {
77 reg = <0x1 0x0 0x2000>;
79 u-boot@0 {
80 reg = <0x0 0x100000>;
85 reg = <0x100000 0x300000>;
88 reg = <0x400000 0x1c00000>;
98 ranges = <0 0xe0000000 0x00100000>;
99 reg = <0xe0000000 0x00000200>;
100 bus-frequency = <0>;
105 reg = <0x200 0x100>;
110 #size-cells = <0>;
111 cell-index = <0>;
113 reg = <0x3000 0x100>;
114 interrupts = <14 0x8>;
119 reg = <0x68>;
126 reg = <0x0a>;
132 cell-index = <0>;
134 reg = <0x7000 0x1000>;
135 interrupts = <16 0x8>;
144 reg = <0x82a8 4>;
145 ranges = <0 0x8100 0x1a8>;
148 cell-index = <0>;
149 dma-channel@0 {
151 reg = <0 0x80>;
152 cell-index = <0>;
158 reg = <0x80 0x80>;
165 reg = <0x100 0x80>;
172 reg = <0x180 0x28>;
181 reg = <0x23000 0x1000>;
183 #size-cells = <0>;
185 interrupts = <38 0x8>;
192 cell-index = <0>;
196 reg = <0x24000 0x1000>;
197 ranges = <0x0 0x24000 0x1000>;
199 interrupts = <32 0x8 33 0x8 34 0x8>;
207 #size-cells = <0>;
209 reg = <0x520 0x20>;
211 phy0: ethernet-phy@0 {
213 interrupts = <20 0x8>;
214 reg = <0x0>;
219 interrupts = <19 0x8>;
220 reg = <0x1>;
224 reg = <0x11>;
237 reg = <0x25000 0x1000>;
238 ranges = <0x0 0x25000 0x1000>;
240 interrupts = <35 0x8 36 0x8 37 0x8>;
248 #size-cells = <0>;
250 reg = <0x520 0x20>;
253 reg = <0x11>;
260 cell-index = <0>;
263 reg = <0x4500 0x100>;
265 interrupts = <9 0x8>;
273 reg = <0x4600 0x100>;
275 interrupts = <10 0x8>;
280 compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0",
282 "fsl,sec2.0";
283 reg = <0x30000 0x10000>;
284 interrupts = <11 0x8>;
288 fsl,exec-units-mask = <0x97c>;
289 fsl,descriptor-types-mask = <0x3a30abf>;
294 reg = <0x18000 0x1000>;
296 interrupts = <44 0x8>;
302 reg = <0x19000 0x1000>;
304 interrupts = <45 0x8>;
310 reg = <0x500 0x100>;
318 reg = <0x600 0x100>;
332 #address-cells = <0>;
334 reg = <0x700 0x100>;
340 reg = <0x7c0 0x40>;
341 msi-available-ranges = <0 0x100>;
342 interrupts = <0x43 0x8
343 0x4 0x8
344 0x51 0x8
345 0x52 0x8
346 0x56 0x8
347 0x57 0x8
348 0x58 0x8
349 0x59 0x8>;
356 reg = <0xb00 0x100 0xa00 0x100>;
364 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
366 /* IDSEL 0x0E -mini PCI */
367 0x7000 0x0 0x0 0x1 &ipic 18 0x8
368 0x7000 0x0 0x0 0x2 &ipic 18 0x8
369 0x7000 0x0 0x0 0x3 &ipic 18 0x8
370 0x7000 0x0 0x0 0x4 &ipic 18 0x8
372 /* IDSEL 0x0F -mini PCI */
373 0x7800 0x0 0x0 0x1 &ipic 17 0x8
374 0x7800 0x0 0x0 0x2 &ipic 17 0x8
375 0x7800 0x0 0x0 0x3 &ipic 17 0x8
376 0x7800 0x0 0x0 0x4 &ipic 17 0x8
378 /* IDSEL 0x10 - PCI slot */
379 0x8000 0x0 0x0 0x1 &ipic 48 0x8
380 0x8000 0x0 0x0 0x2 &ipic 17 0x8
381 0x8000 0x0 0x0 0x3 &ipic 48 0x8
382 0x8000 0x0 0x0 0x4 &ipic 17 0x8>;
384 interrupts = <66 0x8>;
385 bus-range = <0x0 0x0>;
386 ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
387 0x42000000 0 0x80000000 0x80000000 0 0x10000000
388 0x01000000 0 0x00000000 0xe0300000 0 0x00100000>;
393 reg = <0xe0008500 0x100 /* internal registers */
394 0xe0008300 0x8>; /* config space access registers */
405 reg = <0xe0009000 0x00001000>;
406 ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
407 0x01000000 0 0x00000000 0xb1000000 0 0x00800000>;
408 bus-range = <0 255>;
409 interrupt-map-mask = <0xf800 0 0 7>;
410 interrupt-map = <0 0 0 1 &ipic 1 8
411 0 0 0 2 &ipic 1 8
412 0 0 0 3 &ipic 1 8
413 0 0 0 4 &ipic 1 8>;
414 clock-frequency = <0>;
416 pcie@0 {
420 reg = <0 0 0 0 0>;
421 ranges = <0x02000000 0 0xa0000000
422 0x02000000 0 0xa0000000
423 0 0x10000000
424 0x01000000 0 0x00000000
425 0x01000000 0 0x00000000
426 0 0x00800000>;
436 reg = <0xe000a000 0x00001000>;
437 ranges = <0x02000000 0 0xc0000000 0xc0000000 0 0x10000000
438 0x01000000 0 0x00000000 0xd1000000 0 0x00800000>;
439 bus-range = <0 255>;
440 interrupt-map-mask = <0xf800 0 0 7>;
441 interrupt-map = <0 0 0 1 &ipic 2 8
442 0 0 0 2 &ipic 2 8
443 0 0 0 3 &ipic 2 8
444 0 0 0 4 &ipic 2 8>;
445 clock-frequency = <0>;
447 pcie@0 {
451 reg = <0 0 0 0 0>;
452 ranges = <0x02000000 0 0xc0000000
453 0x02000000 0 0xc0000000
454 0 0x10000000
455 0x01000000 0 0x00000000
456 0x01000000 0 0x00000000
457 0 0x00800000>;
465 gpios = <&mcu_pio 0 0>;
470 gpios = <&mcu_pio 1 0>;