Lines Matching +full:0 +full:x3200
29 #size-cells = <0>;
31 PowerPC,8360@0 {
33 reg = <0x0>;
38 timebase-frequency = <0>; /* Filled in by U-Boot */
39 bus-frequency = <0>; /* Filled in by U-Boot */
40 clock-frequency = <0>; /* Filled in by U-Boot */
46 reg = <0 0>; /* Filled in by U-Boot */
54 ranges = <0x0 0xe0000000 0x00200000>;
55 reg = <0xe0000000 0x00000200>;
56 bus-frequency = <0>; /* Filled in by U-Boot */
60 reg = <0xb00 0x100 0xa00 0x100>;
61 interrupts = <80 0x8>;
67 #size-cells = <0>;
68 cell-index = <0>;
70 reg = <0x3000 0x100>;
71 interrupts = <14 0x8>;
77 cell-index = <0>;
80 reg = <0x4500 0x100>;
82 interrupts = <9 0x8>;
90 reg = <0x82a8 4>;
91 ranges = <0 0x8100 0x1a8>;
94 cell-index = <0>;
95 dma-channel@0 {
97 reg = <0 0x80>;
103 reg = <0x80 0x80>;
109 reg = <0x100 0x80>;
115 reg = <0x180 0x28>;
122 #address-cells = <0>;
126 reg = <0x700 0x100>;
131 #size-cells = <0>;
132 reg = <0x1400 0x100>;
140 reg = <0x1430 0x18>;
143 pio_ucc1: ucc_pin@0 {
144 reg = <0>;
148 0 1 3 0 2 0 /* MDIO */
149 0 2 1 0 1 0 /* MDC */
151 0 3 1 0 1 0 /* TxD0 */
152 0 4 1 0 1 0 /* TxD1 */
153 0 5 1 0 1 0 /* TxD2 */
154 0 6 1 0 1 0 /* TxD3 */
155 0 9 2 0 1 0 /* RxD0 */
156 0 10 2 0 1 0 /* RxD1 */
157 0 11 2 0 1 0 /* RxD2 */
158 0 12 2 0 1 0 /* RxD3 */
159 0 7 1 0 1 0 /* TX_EN */
160 0 8 1 0 1 0 /* TX_ER */
161 0 15 2 0 1 0 /* RX_DV */
162 0 16 2 0 1 0 /* RX_ER */
163 0 0 2 0 1 0 /* RX_CLK */
164 2 9 1 0 3 0 /* GTX_CLK - CLK10 */
165 2 8 2 0 1 0 /* GTX125 - CLK9 */
174 0 1 3 0 2 0 /* MDIO */
175 0 2 1 0 1 0 /* MDC */
177 0 17 1 0 1 0 /* TxD0 */
178 0 18 1 0 1 0 /* TxD1 */
179 0 19 1 0 1 0 /* TxD2 */
180 0 20 1 0 1 0 /* TxD3 */
181 0 23 2 0 1 0 /* RxD0 */
182 0 24 2 0 1 0 /* RxD1 */
183 0 25 2 0 1 0 /* RxD2 */
184 0 26 2 0 1 0 /* RxD3 */
185 0 21 1 0 1 0 /* TX_EN */
186 0 22 1 0 1 0 /* TX_ER */
187 0 29 2 0 1 0 /* RX_DV */
188 0 30 2 0 1 0 /* RX_ER */
189 0 31 2 0 1 0 /* RX_CLK */
190 2 2 1 0 2 0 /* GTX_CLK - CLK3 */
191 2 3 2 0 1 0 /* GTX125 - CLK4 */
200 0 1 3 0 2 0 /* MDIO */
201 0 2 1 0 1 0 /* MDC */
203 1 14 1 0 1 0 /* TxD0 (PB14, out, f1) */
204 1 15 1 0 1 0 /* TxD1 (PB15, out, f1) */
205 1 20 2 0 1 0 /* RxD0 (PB20, in, f1) */
206 1 21 2 0 1 0 /* RxD1 (PB21, in, f1) */
207 1 18 1 0 1 0 /* TX_EN (PB18, out, f1) */
208 1 26 2 0 1 0 /* RX_DV (PB26, in, f1) */
209 1 27 2 0 1 0 /* RX_ER (PB27, in, f1) */
211 2 16 2 0 1 0 /* UCC4_RMII_CLK (CLK17) */
220 0 1 3 0 2 0 /* MDIO */
221 0 2 1 0 1 0 /* MDC */
223 3 0 1 0 1 0 /* TxD0 (PD0, out, f1) */
224 3 1 1 0 1 0 /* TxD1 (PD1, out, f1) */
225 3 6 2 0 1 0 /* RxD0 (PD6, in, f1) */
226 3 7 2 0 1 0 /* RxD1 (PD7, in, f1) */
227 3 4 1 0 1 0 /* TX_EN (PD4, out, f1) */
228 3 12 2 0 1 0 /* RX_DV (PD12, in, f1) */
229 3 13 2 0 1 0 /* RX_ER (PD13, in, f1) */
238 0 1 3 0 2 0 /* MDIO */
239 0 2 1 0 1 0 /* MDC */
241 3 14 1 0 1 0 /* TxD0 (PD14, out, f1) */
242 3 15 1 0 1 0 /* TxD1 (PD15, out, f1) */
243 3 20 2 0 1 0 /* RxD0 (PD20, in, f1) */
244 3 21 2 0 1 0 /* RxD1 (PD21, in, f1) */
245 3 18 1 0 1 0 /* TX_EN (PD18, out, f1) */
246 3 26 2 0 1 0 /* RX_DV (PD26, in, f1) */
247 3 27 2 0 1 0 /* RX_ER (PD27, in, f1) */
256 0 1 3 0 2 0 /* MDIO */
257 0 2 1 0 1 0 /* MDC */
259 4 0 1 0 1 0 /* TxD0 (PE0, out, f1) */
260 4 1 1 0 1 0 /* TxD1 (PE1, out, f1) */
261 4 6 2 0 1 0 /* RxD0 (PE6, in, f1) */
262 4 7 2 0 1 0 /* RxD1 (PE7, in, f1) */
263 4 4 1 0 1 0 /* TX_EN (PE4, out, f1) */
264 4 12 2 0 1 0 /* RX_DV (PE12, in, f1) */
265 4 13 2 0 1 0 /* RX_ER (PE13, in, f1) */
274 0 1 3 0 2 0 /* MDIO */
275 0 2 1 0 1 0 /* MDC */
277 4 14 1 0 2 0 /* TxD0 (PE14, out, f2) */
278 4 15 1 0 1 0 /* TxD1 (PE15, out, f1) */
279 4 20 2 0 1 0 /* RxD0 (PE20, in, f1) */
280 4 21 2 0 1 0 /* RxD1 (PE21, in, f1) */
281 4 18 1 0 1 0 /* TX_EN (PE18, out, f1) */
282 4 26 2 0 1 0 /* RX_DV (PE26, in, f1) */
283 4 27 2 0 1 0 /* RX_ER (PE27, in, f1) */
285 2 15 2 0 1 0 /* UCCx_RMII_CLK (CLK16) */
295 ranges = <0x0 0x100000 0x100000>;
296 reg = <0x100000 0x480>;
297 clock-frequency = <0>; /* Filled in by U-Boot */
298 brg-frequency = <0>; /* Filled in by U-Boot */
299 bus-frequency = <0>; /* Filled in by U-Boot */
305 ranges = <0x0 0x00010000 0x0000c000>;
307 data-only@0 {
310 reg = <0x0 0xc000>;
314 /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */
319 reg = <0x2000 0x200>;
330 /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */
335 reg = <0x3000 0x200>;
346 /* Piggy2 (UCC4, MDIO 0x00, RMII) */
351 reg = <0x3200 0x200>;
362 /* Eth-1 (UCC5, MDIO 0x08, RMII) */
367 reg = <0x2400 0x200>;
378 /* Eth-2 (UCC6, MDIO 0x09, RMII) */
383 reg = <0x3400 0x200>;
394 /* Eth-3 (UCC7, MDIO 0x0a, RMII) */
399 reg = <0x2600 0x200>;
410 /* Eth-4 (UCC8, MDIO 0x0b, RMII) */
415 reg = <0x3600 0x200>;
428 #size-cells = <0>;
429 reg = <0x3320 0x18>;
432 /* Piggy2 (UCC4, MDIO 0x00, RMII) */
433 phy_piggy2: ethernet-phy@0 {
434 reg = <0x0>;
437 /* Eth-1 (UCC5, MDIO 0x08, RMII) */
439 reg = <0x08>;
442 /* Eth-2 (UCC6, MDIO 0x09, RMII) */
444 reg = <0x09>;
447 /* Eth-3 (UCC7, MDIO 0x0a, RMII) */
449 reg = <0x0a>;
452 /* Eth-4 (UCC8, MDIO 0x0b, RMII) */
454 reg = <0x0b>;
457 /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */
460 interrupts = <17 0x8>;
461 reg = <0x10>;
464 /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */
467 interrupts = <18 0x8>;
468 reg = <0x11>;
475 #address-cells = <0>;
477 reg = <0x80 0x80>;
480 32 0x8
481 33 0x8
482 34 0x8
483 35 0x8
484 40 0x8
485 41 0x8
486 42 0x8
487 43 0x8
499 reg = <0xe0005000 0xd8>;
500 ranges = <0 0 0xf0000000 0x04000000 /* LB 0 */
501 1 0 0xe8000000 0x01000000 /* LB 1 */
502 3 0 0xa0000000 0x10000000>; /* LB 3 */
504 flash@0,0 {
506 reg = <0 0 0x04000000>;
510 partition@0 { /* 768KB */
512 reg = <0 0xC0000>;
516 reg = <0xC0000 0x20000>;
520 reg = <0xE0000 0x20000>;
524 reg = <0x100000 0x3F00000>;