Lines Matching +full:0 +full:x08010000
18 dcr-parent = <&{/cpus/cpu@0}>;
31 #size-cells = <0>;
33 cpu@0 {
36 reg = <0x00000000>;
37 clock-frequency = <0>; /* Filled in by U-Boot */
38 timebase-frequency = <0>; /* Filled in by U-Boot */
51 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
57 cell-index = <0>;
58 dcr-reg = <0x0c0 0x009>;
59 #address-cells = <0>;
60 #size-cells = <0>;
68 dcr-reg = <0x0d0 0x009>;
69 #address-cells = <0>;
70 #size-cells = <0>;
72 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
80 dcr-reg = <0x0e0 0x009>;
81 #address-cells = <0>;
82 #size-cells = <0>;
84 interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
92 dcr-reg = <0x0f0 0x009>;
93 #address-cells = <0>;
94 #size-cells = <0>;
96 interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
102 dcr-reg = <0x00e 0x002>;
107 dcr-reg = <0x00c 0x002>;
112 dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */
113 0x030 0x008>; /* L2 cache DCR's */
125 clock-frequency = <0>; /* Filled in by U-Boot */
129 dcr-reg = <0x010 0x002>;
135 reg = <4 0x00180000 0x80400>;
137 interrupts = <0x1d 0x4>;
142 reg = <4 0x00110000 0x50>;
147 dcr-reg = <0x180 0x062>;
150 #address-cells = <0>;
151 #size-cells = <0>;
153 interrupts = < /*TXEOB*/ 0x6 0x4
154 /*RXEOB*/ 0x7 0x4
155 /*SERR*/ 0x3 0x4
156 /*TXDE*/ 0x4 0x4
157 /*RXDE*/ 0x5 0x4>;
158 desc-base-addr-high = <0x8>;
165 ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
166 clock-frequency = <0>; /* Filled in by U-Boot */
170 dcr-reg = <0x012 0x002>;
173 clock-frequency = <0>; /* Filled in by U-Boot */
175 interrupts = <0x6 0x4>;
178 nor_flash@0,0 {
181 reg = <0x00000000 0x00000000 0x04000000>;
184 partition@0 {
186 reg = <0x00000000 0x001e0000>;
190 reg = <0x001e0000 0x00020000>;
194 reg = <0x00200000 0x01400000>;
198 reg = <0x01600000 0x00400000>;
202 reg = <0x01a00000 0x02560000>;
206 reg = <0x03f60000 0x00040000>;
210 reg = <0x03fa0000 0x00060000>;
214 ndfc@3,0 {
216 reg = <0x00000003 0x00000000 0x00002000>;
217 ccr = <0x00001000>;
218 bank-settings = <0x80002222>;
226 partition@0 {
228 reg = <0x00000000 0x00100000>;
232 reg = <0x00000000 0x03f00000>;
241 reg = <0xef600300 0x00000008>;
242 virtual-reg = <0xef600300>;
243 clock-frequency = <0>; /* Filled in by U-Boot */
244 current-speed = <0>; /* Filled in by U-Boot */
246 interrupts = <0x1 0x4>;
252 reg = <0xef600400 0x00000008>;
253 virtual-reg = <0xef600400>;
254 clock-frequency = <0>; /* Filled in by U-Boot */
255 current-speed = <0>; /* Filled in by U-Boot */
257 interrupts = <0x1 0x4>;
263 reg = <0xef600500 0x00000008>;
264 virtual-reg = <0xef600500>;
265 clock-frequency = <0>; /* Filled in by U-Boot */
266 current-speed = <0>; /* Filled in by U-Boot */
268 interrupts = <28 0x4>;
274 reg = <0xef600600 0x00000008>;
275 virtual-reg = <0xef600600>;
276 clock-frequency = <0>; /* Filled in by U-Boot */
277 current-speed = <0>; /* Filled in by U-Boot */
279 interrupts = <29 0x4>;
284 reg = <0xef600700 0x00000014>;
286 interrupts = <0x2 0x4>;
288 #size-cells = <0>;
291 reg = <0x68>;
293 interrupts = <0x19 0x8>;
297 reg = <0x48>;
299 interrupts = <0x14 0x8>;
305 reg = <0xef600800 0x00000014>;
307 interrupts = <0x3 0x4>;
312 reg = <0xef600d00 0x0000000c>;
317 reg = <0xef601500 0x00000008>;
323 reg = <0xef601600 0x00000008>;
329 reg = <0xef601350 0x00000030>;
334 reg = <0xef601450 0x00000030>;
341 interrupts = <0x0 0x1>;
343 #address-cells = <0>;
344 #size-cells = <0>;
345 interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
346 /*Wake*/ 0x1 &UIC2 0x14 0x4>;
347 reg = <0xef600e00 0x000000c4>;
350 mal-tx-channel = <0>;
351 mal-rx-channel = <0>;
352 cell-index = <0>;
358 phy-map = <0x00000000>;
360 rgmii-channel = <0>;
362 tah-channel = <0>;
371 interrupts = <0x0 0x1>;
373 #address-cells = <0>;
374 #size-cells = <0>;
375 interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
376 /*Wake*/ 0x1 &UIC2 0x15 0x4>;
377 reg = <0xef600f00 0x000000c4>;
388 phy-map = <0x00000000>;
402 interrupts = <0x0 0x1>;
404 #address-cells = <0>;
405 #size-cells = <0>;
406 interrupt-map = </*Status*/ 0x0 &UIC2 0x12 0x4
407 /*Wake*/ 0x1 &UIC2 0x16 0x4>;
408 reg = <0xef601100 0x000000c4>;
420 phy-map = <0x00000000>;
422 rgmii-channel = <0>;
432 interrupts = <0x0 0x1>;
434 #address-cells = <0>;
435 #size-cells = <0>;
436 interrupt-map = </*Status*/ 0x0 &UIC2 0x13 0x4
437 /*Wake*/ 0x1 &UIC2 0x17 0x4>;
438 reg = <0xef601200 0x000000c4>;
450 phy-map = <0x00000000>;
468 reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */
469 0x00000000 0x00000000 0x00000000 /* no IACK cycles */
470 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */
471 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */
472 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */
477 ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
478 0x02000000 0x00000000 0x00000000 0x0000000c 0x0ee00000 0x00000000 0x00100000
479 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;
481 /* Inbound 2GB range starting at 0 */
482 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
484 /* This drives busses 0 to 0x3f */
485 bus-range = <0x0 0x3f>;
487 /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
488 interrupt-map-mask = <0x0 0x0 0x0 0x0>;
489 interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >;
499 port = <0x0>; /* port number */
500 reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
501 0x0000000c 0x08010000 0x00001000>; /* Registers */
502 dcr-reg = <0x100 0x020>;
503 sdr-base = <0x300>;
508 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
509 0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000
510 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
512 /* Inbound 2GB range starting at 0 */
513 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
515 /* This drives busses 40 to 0x7f */
516 bus-range = <0x40 0x7f>;
524 * The real slot is on idsel 0, so the swizzling is 1:1
526 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
528 0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */
529 0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */
530 0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
531 0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;
541 port = <0x1>; /* port number */
542 reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */
543 0x0000000c 0x08011000 0x00001000>; /* Registers */
544 dcr-reg = <0x120 0x020>;
545 sdr-base = <0x340>;
550 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
551 0x02000000 0x00000000 0x00000000 0x0000000f 0x00100000 0x00000000 0x00100000
552 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
554 /* Inbound 2GB range starting at 0 */
555 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
557 /* This drives busses 80 to 0xbf */
558 bus-range = <0x80 0xbf>;
566 * The real slot is on idsel 0, so the swizzling is 1:1
568 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
570 0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */
571 0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */
572 0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */
573 0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>;