dts/fsl/t104xqds.dtsi

4  * Copyright 2013 - 2015 Freescale Semiconductor Inc.
37 	#address-cells = <2>;
38 	#size-cells = <2>;
39 	interrupt-parent = <&mpic>;
68 	reserved-memory {
69 		#address-cells = <2>;
70 		#size-cells = <2>;
73 		bman_fbpr: bman-fbpr {
77 		qman_fqd: qman-fqd {
81 		qman_pfdr: qman-pfdr {
94 			#address-cells = <1>;
95 			#size-cells = <1>;
96 			compatible = "cfi-flash";
99 			bank-width = <2>;
100 			device-width = <1>;
104 			#address-cells = <1>;
105 			#size-cells = <1>;
106 			compatible = "fsl,ifc-nand";
110 		board-control@3,0 {
111 			#address-cells = <1>;
112 			#size-cells = <1>;
113 			compatible = "fsl,fpga-qixis";
117 			mdio-mux-emi1 {
118 				#address-cells = <1>;
119 				#size-cells = <0>;
120 				compatible = "mdio-mux-mmioreg", "mdio-mux";
121 				mdio-parent-bus = <&mdio0>;
123 				mux-mask = <0xe0>;
125 				t1040mdio0: mdio@0 {
126 					#address-cells = <1>;
127 					#size-cells = <0>;
131 					rgmii_phy1: ethernet-phy@1 {
136 				t1040mdio1: mdio@20 {
137 					#address-cells = <1>;
138 					#size-cells = <0>;
142 					rgmii_phy2: ethernet-phy@2 {
147 				t1040mdio3: mdio@60 {
148 					#address-cells = <1>;
149 					#size-cells = <0>;
153 					phy_s3_01: ethernet-phy@1c {
157 					phy_s3_02: ethernet-phy@1d {
161 					phy_s3_03: ethernet-phy@1e {
165 					phy_s3_04: ethernet-phy@1f {
170 				t1040mdio5: mdio@a0 {
171 					#address-cells = <1>;
172 					#size-cells = <0>;
175 					phy_s5_01: ethernet-phy@1c {
179 					phy_s5_02: ethernet-phy@1d {
183 					phy_s5_03: ethernet-phy@1e {
187 					phy_s5_04: ethernet-phy@1f {
192 				t1040mdio6: mdio@c0 {
193 					#address-cells = <1>;
194 					#size-cells = <0>;
197 					phy_s6_01: ethernet-phy@1c {
201 					phy_s6_02: ethernet-phy@1d {
205 					phy_s6_03: ethernet-phy@1e {
209 					phy_s6_04: ethernet-phy@1f {
214 				t1040mdio7: mdio@e0 {
215 					#address-cells = <1>;
216 					#size-cells = <0>;
220 					phy_s7_01: ethernet-phy@1c {
224 					phy_s7_02: ethernet-phy@1d {
228 					phy_s7_03: ethernet-phy@1e {
232 					phy_s7_04: ethernet-phy@1f {
248 	bportals: bman-portals@ff4000000 {
252 	qportals: qman-portals@ff6000000 {
262 				#address-cells = <1>;
263 				#size-cells = <1>;
264 				compatible = "micron,n25q128a11", "jedec,spi-nor";
266 				spi-max-frequency = <10000000>; /* input clock */
271 			i2c-mux@77 {
284 				fixed-link = <0 1 1000 0 0>;
285 				phy-connection-type = "sgmii";
289 				fixed-link = <1 1 1000 0 0>;
290 				phy-connection-type = "sgmii";
294 				phy-handle = <&phy_s7_03>;
295 				phy-connection-type = "sgmii";
299 				phy-handle = <&rgmii_phy1>;
300 				phy-connection-type = "rgmii";
304 				phy-handle = <&rgmii_phy2>;
305 				phy-connection-type = "rgmii";
373 		brg-frequency = <0>;
374 		bus-frequency = <0>;
377 			compatible = "fsl,t1040-qe-si";
382 			compatible = "fsl,t1040-qe-siram";
387 			compatible = "fsl,ucc-hdlc";
388 			rx-clock-name = "clk8";
389 			tx-clock-name = "clk9";
390 			fsl,rx-sync-clock = "rsync_pin";
391 			fsl,tx-sync-clock = "tsync_pin";
392 			fsl,tx-timeslot-mask = <0xfffffffe>;
393 			fsl,rx-timeslot-mask = <0xfffffffe>;
394 			fsl,tdm-framer-type = "e1";
395 			fsl,tdm-id = <0>;
396 			fsl,siram-entry-id = <0>;
397 			fsl,tdm-interface;
401 			compatible = "fsl,t1040-ucc-uart";
402 			port-number = <0>;
403 			rx-clock-name = "brg2";
404 			tx-clock-name = "brg2";