Lines Matching +full:pcs +full:- +full:handle
4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
37 cell-index = <0x9>;
38 compatible = "fsl,fman-v3-port-rx";
40 fsl,fman-10g-port;
41 fsl,fman-best-effort-port;
45 cell-index = <0x29>;
46 compatible = "fsl,fman-v3-port-tx";
48 fsl,fman-10g-port;
49 fsl,fman-best-effort-port;
53 cell-index = <1>;
54 compatible = "fsl,fman-memac";
56 fsl,fman-ports = <&fman0_rx_0x09 &fman0_tx_0x29>;
57 ptp-timer = <&ptp_timer0>;
58 pcsphy-handle = <&pcsphy1>, <&qsgmiia_pcs1>;
59 pcs-handle-names = "sgmii", "qsgmii";
63 qsgmiia_pcs1: ethernet-pcs@1 {
64 compatible = "fsl,lynx-pcs";
70 #address-cells = <1>;
71 #size-cells = <0>;
72 compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
74 fsl,erratum-a011043; /* must ignore read errors */
76 pcsphy1: ethernet-phy@0 {