Lines Matching +full:0 +full:x12000000
80 size = <0 0x1000000>;
81 alignment = <0 0x1000000>;
84 size = <0 0x400000>;
85 alignment = <0 0x400000>;
88 size = <0 0x2000000>;
89 alignment = <0 0x2000000>;
94 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
98 ranges = <0x0 0xf 0xf4000000 0x200000>;
102 ranges = <0x0 0xf 0xf4200000 0x200000>;
106 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
107 reg = <0xf 0xfe000000 0 0x00001000>;
109 flash@0 {
113 reg = <0>;
117 reg = <0x00000000 0x00100000>;
121 reg = <0x00100000 0x00500000>;
125 reg = <0x00600000 0x00100000>;
129 reg = <0x00700000 0x00900000>;
137 reg = <0x51>;
141 reg = <0x52>;
148 reg = <0x68>;
149 interrupts = <0x1 0x1 0 0>;
153 reg = <0x40>;
158 reg = <0x41>;
163 reg = <0x44>;
168 reg = <0x45>;
173 reg = <0x4c>;
235 reg = <0xf 0xfe124000 0 0x1000>;
236 ranges = <0 0 0xf 0xe8000000 0x08000000
237 2 0 0xf 0xffa00000 0x00040000
238 3 0 0xf 0xffdf0000 0x00008000>;
240 flash@0,0 {
242 reg = <0 0 0x08000000>;
247 nand@2,0 {
251 reg = <0x2 0x0 0x40000>;
253 partition@0 {
255 reg = <0x0 0x02000000>;
260 reg = <0x02000000 0x10000000>;
265 reg = <0x12000000 0x08000000>;
270 reg = <0x1a000000 0x04000000>;
275 reg = <0x1e000000 0x01000000>;
280 reg = <0x1f000000 0x01000000>;
284 board-control@3,0 {
288 reg = <3 0 0x40>;
289 ranges = <0 3 0 0x40>;
293 #size-cells = <0>;
297 mux-mask = <0x78>;
301 #size-cells = <0>;
305 phy_rgmii_0: ethernet-phy@0 {
306 reg = <0x0>;
310 reg = <0x1>;
316 #size-cells = <0>;
317 reg = <0x28>;
321 reg = <0x1c>;
325 reg = <0x1d>;
329 reg = <0x1e>;
333 reg = <0x1f>;
339 #size-cells = <0>;
340 reg = <0x68>;
344 reg = <0x1c>;
348 reg = <0x1d>;
352 reg = <0x1e>;
356 reg = <0x1f>;
362 #size-cells = <0>;
363 reg = <0x38>;
367 reg = <0x1c>;
371 reg = <0x1d>;
375 reg = <0x1e>;
379 reg = <0x1f>;
384 #size-cells = <0>;
385 reg = <0x48>;
389 reg = <0x1c>;
393 reg = <0x1d>;
397 reg = <0x1e>;
401 reg = <0x1f>;
408 #size-cells = <0>;
412 mux-mask = <0x06>;
414 hydra_xg_slot1: hydra-xg-slot1@0 {
416 #size-cells = <0>;
417 reg = <0>;
420 phy_xgmii_slot_1: ethernet-phy@0 {
428 #size-cells = <0>;
433 reg = <0>;
441 reg = <0xf 0xfe200000 0 0x1000>;
442 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
443 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
444 pcie@0 {
445 ranges = <0x02000000 0 0xe0000000
446 0x02000000 0 0xe0000000
447 0 0x20000000
449 0x01000000 0 0x00000000
450 0x01000000 0 0x00000000
451 0 0x00010000>;
456 reg = <0xf 0xfe201000 0 0x1000>;
457 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
458 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
459 pcie@0 {
460 ranges = <0x02000000 0 0xe0000000
461 0x02000000 0 0xe0000000
462 0 0x20000000
464 0x01000000 0 0x00000000
465 0x01000000 0 0x00000000
466 0 0x00010000>;
471 reg = <0xf 0xfe202000 0 0x1000>;
472 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
473 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
474 pcie@0 {
475 ranges = <0x02000000 0 0xe0000000
476 0x02000000 0 0xe0000000
477 0 0x20000000
479 0x01000000 0 0x00000000
480 0x01000000 0 0x00000000
481 0 0x00010000>;