Lines Matching +full:tbi +full:- +full:handle
2 * P1025 TWR Device Tree Source stub (no addresses or top-level ranges)
44 #address-cells = <1>;
45 #size-cells = <1>;
46 compatible = "cfi-flash";
48 bank-width = <2>;
49 device-width = <1>;
55 label = "NOR Vitesse-7385 Firmware";
56 read-only;
82 read-only;
87 /* 512KB for u-boot Bootloader Image */
88 /* 512KB for u-boot Environment Variables */
90 label = "NOR U-Boot Image";
91 read-only;
109 phy0: ethernet-phy@2 {
110 interrupt-parent = <&mpic>;
115 phy1: ethernet-phy@1 {
116 interrupt-parent = <&mpic>;
121 tbi0: tbi-phy@11 {
123 device_type = "tbi-phy";
128 tbi1: tbi-phy@11 {
130 device_type = "tbi-phy";
135 tbi2: tbi-phy@11 {
137 device_type = "tbi-phy";
142 compatible = "fsl,etsec-ptp";
145 fsl,tclk-period = <10>;
146 fsl,tmr-prsc = <2>;
147 fsl,tmr-add = <0xc0000021>;
148 fsl,tmr-fiper1 = <999999990>;
149 fsl,tmr-fiper2 = <99990>;
150 fsl,max-adj = <133333332>;
154 phy-handle = <&phy0>;
155 phy-connection-type = "rgmii-id";
164 phy-handle = <&phy1>;
165 phy-connection-type = "rgmii-id";
169 #address-cells = <1>;
170 #size-cells = <1>;
174 num-ports = <3>;
176 pio-map = <
199 pio-map = <
214 pio-map = <
224 pio-map = <
239 rx-clock-name = "clk12";
240 tx-clock-name = "clk9";
241 pio-handle = <&pio1>;
242 phy-handle = <&qe_phy0>;
243 phy-connection-type = "mii";
247 qe_phy0: ethernet-phy@18 {
248 interrupt-parent = <&mpic>;
251 device_type = "ethernet-phy";
253 qe_phy1: ethernet-phy@19 {
254 interrupt-parent = <&mpic>;
257 device_type = "ethernet-phy";
259 tbi-phy@11 {
261 device_type = "tbi-phy";
268 rx-clock-name = "none";
269 tx-clock-name = "clk13";
270 pio-handle = <&pio2>;
271 phy-handle = <&qe_phy1>;
272 phy-connection-type = "rmii";
278 port-number = <0>;
279 rx-clock-name = "brg6";
280 tx-clock-name = "brg6";
281 pio-handle = <&pio3>;
287 port-number = <1>;
288 rx-clock-name = "brg2";
289 tx-clock-name = "brg2";
290 pio-handle = <&pio4>;